Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15529

1

T3

8

T5

10

T11

2

auto[1]

11223

1

T13

129

T16

20

T17

161

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3291	1			T13	20		T17	40		T39	26
values[1]	3501	1			T17	42		T33	21		T35	66
values[2]	2810	1			T13	64		T16	20		T17	21
values[3]	3959	1			T13	104		T17	75		T18	20
values[4]	2709	1			T3	8		T18	29		T30	2
values[5]	4133	1			T13	45		T17	64		T33	20
values[6]	2985	1			T13	40		T17	28		T33	20
values[7]	3364	1			T5	10		T11	2		T13	45

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2972	1			T13	22		T17	20		T30	2
values[1]	3209	1			T3	8		T17	95		T33	20
values[2]	3316	1			T11	2		T13	60		T17	65
values[3]	3469	1			T13	108		T39	26		T19	172
values[4]	3074	1			T17	42		T33	42		T97	10
values[5]	3504	1			T13	48		T16	20		T33	25
values[6]	3569	1			T13	38		T17	20		T33	120
values[7]	3639	1			T5	10		T13	42		T17	80

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	234	1			T35	12		T120	15		T163	18
auto[0]	values[0]	values[1]	347	1			T17	12		T35	15		T291	10
auto[0]	values[0]	values[2]	231	1			T13	13		T19	15		T147	13
auto[0]	values[0]	values[3]	354	1			T39	26		T19	9		T177	14
auto[0]	values[0]	values[4]	247	1			T153	4		T175	14		T120	14
auto[0]	values[0]	values[5]	355	1			T36	13		T202	2		T147	178
auto[0]	values[0]	values[6]	182	1			T148	16		T292	24		T293	10
auto[0]	values[0]	values[7]	113	1			T17	12		T20	9		T154	8
auto[0]	values[1]	values[0]	205	1			T35	14		T151	10		T194	20
auto[0]	values[1]	values[1]	168	1			T35	13		T36	9		T198	10
auto[0]	values[1]	values[2]	183	1			T166	2		T19	29		T20	12
auto[0]	values[1]	values[3]	172	1			T280	2		T20	14		T148	14
auto[0]	values[1]	values[4]	434	1			T17	11		T181	177		T32	27
auto[0]	values[1]	values[5]	299	1			T36	9		T20	14		T81	8
auto[0]	values[1]	values[6]	234	1			T17	13		T33	14		T264	10
auto[0]	values[1]	values[7]	322	1			T19	15		T151	12		T191	2
auto[0]	values[2]	values[0]	159	1			T36	14		T20	12		T161	12
auto[0]	values[2]	values[1]	174	1			T294	2		T178	66		T152	9
auto[0]	values[2]	values[2]	260	1			T13	15		T17	12		T36	11
auto[0]	values[2]	values[3]	232	1			T13	15		T295	46		T222	23
auto[0]	values[2]	values[4]	124	1			T19	9		T154	11		T226	7
auto[0]	values[2]	values[5]	271	1			T148	10		T154	8		T155	38
auto[0]	values[2]	values[6]	113	1			T33	37		T19	11		T20	12
auto[0]	values[2]	values[7]	196	1			T13	10		T179	22		T163	9
auto[0]	values[3]	values[0]	250	1			T19	30		T151	11		T200	24
auto[0]	values[3]	values[1]	305	1			T17	12		T33	7		T19	16
auto[0]	values[3]	values[2]	254	1			T18	11		T268	12		T187	14
auto[0]	values[3]	values[3]	261	1			T13	54		T19	29		T192	6
auto[0]	values[3]	values[4]	281	1			T33	17		T272	12		T151	10
auto[0]	values[3]	values[5]	211	1			T33	11		T164	20		T296	12
auto[0]	values[3]	values[6]	474	1			T13	9		T33	10		T34	11
auto[0]	values[3]	values[7]	310	1			T35	14		T19	21		T20	24
auto[0]	values[4]	values[0]	236	1			T30	2		T149	13		T169	10
auto[0]	values[4]	values[1]	213	1			T3	8		T297	22		T149	13
auto[0]	values[4]	values[2]	139	1			T18	25		T139	57		T298	12
auto[0]	values[4]	values[3]	227	1			T19	28		T20	15		T158	10
auto[0]	values[4]	values[4]	146	1			T35	27		T36	11		T32	13
auto[0]	values[4]	values[5]	144	1			T189	10		T154	21		T299	14
auto[0]	values[4]	values[6]	276	1			T33	11		T19	12		T173	10
auto[0]	values[4]	values[7]	154	1			T33	32		T19	11		T20	16
auto[0]	values[5]	values[0]	396	1			T35	9		T151	38		T224	11
auto[0]	values[5]	values[1]	220	1			T35	8		T32	13		T232	13
auto[0]	values[5]	values[2]	432	1			T17	37		T300	43		T186	15
auto[0]	values[5]	values[3]	258	1			T19	24		T150	4		T148	14
auto[0]	values[5]	values[4]	372	1			T17	6		T19	11		T171	43
auto[0]	values[5]	values[5]	234	1			T13	17		T34	14		T36	11
auto[0]	values[5]	values[6]	270	1			T286	18		T229	14		T301	8
auto[0]	values[5]	values[7]	282	1			T13	10		T33	7		T36	13
auto[0]	values[6]	values[0]	120	1			T146	4		T35	25		T19	13
auto[0]	values[6]	values[1]	182	1			T188	14		T148	6		T227	13
auto[0]	values[6]	values[2]	235	1			T13	10		T36	71		T232	26
auto[0]	values[6]	values[3]	171	1			T13	12		T20	16		T148	11
auto[0]	values[6]	values[4]	110	1			T33	10		T148	17		T224	42
auto[0]	values[6]	values[5]	286	1			T34	10		T302	2		T186	21
auto[0]	values[6]	values[6]	284	1			T36	14		T155	11		T222	8
auto[0]	values[6]	values[7]	352	1			T17	12		T36	14		T186	16
auto[0]	values[7]	values[0]	273	1			T13	11		T17	9		T19	36
auto[0]	values[7]	values[1]	237	1			T34	13		T32	41		T120	11
auto[0]	values[7]	values[2]	310	1			T11	2		T33	12		T183	6
auto[0]	values[7]	values[3]	151	1			T303	2		T304	10		T147	13
auto[0]	values[7]	values[4]	120	1			T83	8		T147	4		T155	31
auto[0]	values[7]	values[5]	141	1			T13	13		T19	10		T305	8
auto[0]	values[7]	values[6]	151	1			T34	13		T36	12		T32	19
auto[0]	values[7]	values[7]	452	1			T5	10		T17	25		T306	12
auto[1]	values[0]	values[0]	162	1			T35	8		T120	41		T163	9
auto[1]	values[0]	values[1]	244	1			T17	8		T35	9		T148	9
auto[1]	values[0]	values[2]	156	1			T13	7		T159	2		T19	5
auto[1]	values[0]	values[3]	110	1			T19	20		T186	4		T120	10
auto[1]	values[0]	values[4]	234	1			T120	6		T189	8		T44	7
auto[1]	values[0]	values[5]	171	1			T36	54		T147	2		T32	27
auto[1]	values[0]	values[6]	73	1			T148	4		T204	10		T285	6
auto[1]	values[0]	values[7]	78	1			T17	8		T20	12		T154	12
auto[1]	values[1]	values[0]	175	1			T35	32		T151	10		T147	12
auto[1]	values[1]	values[1]	139	1			T35	7		T36	11		T139	15
auto[1]	values[1]	values[2]	145	1			T19	41		T20	8		T171	4
auto[1]	values[1]	values[3]	269	1			T20	9		T148	11		T226	74
auto[1]	values[1]	values[4]	133	1			T17	11		T32	10		T148	10
auto[1]	values[1]	values[5]	254	1			T36	19		T20	6		T147	8
auto[1]	values[1]	values[6]	171	1			T17	7		T33	7		T147	17
auto[1]	values[1]	values[7]	198	1			T19	15		T151	8		T176	2
auto[1]	values[2]	values[0]	28	1			T36	6		T20	8		T147	2
auto[1]	values[2]	values[1]	73	1			T178	8		T152	11		T234	22
auto[1]	values[2]	values[2]	249	1			T13	5		T17	9		T36	57
auto[1]	values[2]	values[3]	174	1			T13	7		T222	28		T196	24
auto[1]	values[2]	values[4]	209	1			T19	29		T154	9		T226	13
auto[1]	values[2]	values[5]	173	1			T16	20		T148	10		T154	18
auto[1]	values[2]	values[6]	249	1			T33	18		T19	15		T20	12
auto[1]	values[2]	values[7]	126	1			T13	12		T163	17		T178	9
auto[1]	values[3]	values[0]	110	1			T19	4		T151	20		T120	10
auto[1]	values[3]	values[1]	184	1			T17	63		T33	13		T19	13
auto[1]	values[3]	values[2]	201	1			T18	9		T206	18		T147	5
auto[1]	values[3]	values[3]	175	1			T13	12		T19	17		T32	20
auto[1]	values[3]	values[4]	317	1			T33	5		T97	10		T151	54
auto[1]	values[3]	values[5]	101	1			T33	14		T158	8		T307	5
auto[1]	values[3]	values[6]	338	1			T13	29		T33	14		T34	9
auto[1]	values[3]	values[7]	187	1			T35	12		T19	8		T20	29
auto[1]	values[4]	values[0]	137	1			T149	7		T186	6		T120	6
auto[1]	values[4]	values[1]	138	1			T149	7		T120	17		T180	4
auto[1]	values[4]	values[2]	120	1			T18	4		T139	6		T195	34
auto[1]	values[4]	values[3]	259	1			T19	12		T20	5		T217	8
auto[1]	values[4]	values[4]	78	1			T35	19		T36	9		T32	16
auto[1]	values[4]	values[5]	143	1			T40	20		T189	10		T154	7
auto[1]	values[4]	values[6]	162	1			T33	9		T19	9		T44	8
auto[1]	values[4]	values[7]	137	1			T33	8		T19	13		T20	6
auto[1]	values[5]	values[0]	219	1			T35	25		T151	10		T224	9
auto[1]	values[5]	values[1]	226	1			T35	28		T32	9		T232	7
auto[1]	values[5]	values[2]	159	1			T17	7		T193	4		T162	18
auto[1]	values[5]	values[3]	292	1			T19	33		T148	9		T232	20
auto[1]	values[5]	values[4]	142	1			T17	14		T19	10		T308	14
auto[1]	values[5]	values[5]	201	1			T13	8		T34	6		T36	65
auto[1]	values[5]	values[6]	140	1			T229	45		T234	8		T210	12
auto[1]	values[5]	values[7]	290	1			T13	10		T33	13		T36	79
auto[1]	values[6]	values[0]	90	1			T35	12		T19	7		T32	21
auto[1]	values[6]	values[1]	196	1			T148	18		T227	9		T195	70
auto[1]	values[6]	values[2]	140	1			T13	10		T36	9		T232	9
auto[1]	values[6]	values[3]	156	1			T13	8		T20	4		T148	10
auto[1]	values[6]	values[4]	73	1			T33	10		T148	37		T224	7
auto[1]	values[6]	values[5]	241	1			T34	11		T186	12		T232	10
auto[1]	values[6]	values[6]	130	1			T36	14		T155	9		T222	12
auto[1]	values[6]	values[7]	219	1			T17	16		T36	6		T186	11
auto[1]	values[7]	values[0]	178	1			T13	11		T17	11		T19	11
auto[1]	values[7]	values[1]	163	1			T34	12		T32	22		T120	17
auto[1]	values[7]	values[2]	102	1			T33	8		T189	5		T226	13
auto[1]	values[7]	values[3]	208	1			T147	114		T178	13		T234	9
auto[1]	values[7]	values[4]	54	1			T147	16		T199	4		T155	17
auto[1]	values[7]	values[5]	279	1			T13	10		T19	22		T120	7
auto[1]	values[7]	values[6]	322	1			T34	62		T36	8		T32	4
auto[1]	values[7]	values[7]	223	1			T17	7		T186	18		T120	3