Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2370230	1			T1	2		T2	20028		T3	1
all_pins[1]	2370230	1			T1	2		T2	20028		T3	1
all_pins[2]	2370230	1			T1	2		T2	20028		T3	1
all_pins[3]	2370230	1			T1	2		T2	20028		T3	1
all_pins[4]	2370230	1			T1	2		T2	20028		T3	1
all_pins[5]	2370230	1			T1	2		T2	20028		T3	1
all_pins[6]	2370230	1			T1	2		T2	20028		T3	1
all_pins[7]	2370230	1			T1	2		T2	20028		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18879523	1			T1	16		T2	160224		T3	8
values[0x1]	82317	1			T14	23		T17	32		T19	23399
transitions[0x0=>0x1]	80228	1			T14	17		T17	24		T19	22757
transitions[0x1=>0x0]	80244	1			T14	17		T17	24		T19	22757

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2369999	1			T1	2		T2	20028		T3	1
all_pins[0]	values[0x1]	231	1			T14	6		T17	3		T19	1
all_pins[0]	transitions[0x0=>0x1]	189	1			T14	4		T17	3		T127	1
all_pins[0]	transitions[0x1=>0x0]	282	1			T14	1		T17	4		T19	1
all_pins[1]	values[0x0]	2369906	1			T1	2		T2	20028		T3	1
all_pins[1]	values[0x1]	324	1			T14	3		T17	4		T19	2
all_pins[1]	transitions[0x0=>0x1]	257	1			T14	1		T17	1		T19	1
all_pins[1]	transitions[0x1=>0x0]	170	1			T14	3		T17	2		T19	7
all_pins[2]	values[0x0]	2369993	1			T1	2		T2	20028		T3	1
all_pins[2]	values[0x1]	237	1			T14	5		T17	5		T19	8
all_pins[2]	transitions[0x0=>0x1]	182	1			T14	5		T17	3		T19	8
all_pins[2]	transitions[0x1=>0x0]	153	1			T17	2		T19	2		T21	3
all_pins[3]	values[0x0]	2370022	1			T1	2		T2	20028		T3	1
all_pins[3]	values[0x1]	208	1			T17	4		T19	2		T127	1
all_pins[3]	transitions[0x0=>0x1]	152	1			T17	4		T19	2		T21	4
all_pins[3]	transitions[0x1=>0x0]	160	1			T14	2		T17	3		T19	1
all_pins[4]	values[0x0]	2370014	1			T1	2		T2	20028		T3	1
all_pins[4]	values[0x1]	216	1			T14	2		T17	3		T19	1
all_pins[4]	transitions[0x0=>0x1]	165	1			T14	2		T17	3		T19	1
all_pins[4]	transitions[0x1=>0x0]	1935	1			T14	1		T17	4		T19	637
all_pins[5]	values[0x0]	2368244	1			T1	2		T2	20028		T3	1
all_pins[5]	values[0x1]	1986	1			T14	1		T17	4		T19	637
all_pins[5]	transitions[0x0=>0x1]	290	1			T14	1		T17	3		T19	1
all_pins[5]	transitions[0x1=>0x0]	77193	1			T17	4		T19	22109		T127	4
all_pins[6]	values[0x0]	2291341	1			T1	2		T2	20028		T3	1
all_pins[6]	values[0x1]	78889	1			T17	5		T19	22745		T127	4
all_pins[6]	transitions[0x0=>0x1]	78826	1			T17	4		T19	22742		T127	4
all_pins[6]	transitions[0x1=>0x0]	163	1			T14	6		T17	3		T21	1
all_pins[7]	values[0x0]	2370004	1			T1	2		T2	20028		T3	1
all_pins[7]	values[0x1]	226	1			T14	6		T17	4		T19	3
all_pins[7]	transitions[0x0=>0x1]	167	1			T14	4		T17	3		T19	2
all_pins[7]	transitions[0x1=>0x0]	188	1			T14	4		T17	2		T127	1