Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	352	1			T11	2		T13	4		T17	2
auto[ReadAddrCrossIntoMailbox]	235	1			T13	4		T17	3		T33	2
auto[ReadAddrCrossOutOfMailbox]	260	1			T13	2		T17	4		T18	1
auto[ReadAddrCrossAllMailbox]	161	1			T13	2		T17	2		T33	3
auto[ReadAddrOutsideMailbox]	2835	1			T3	2		T13	36		T16	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1932

1

T3

1

T11

1

T13

22

auto[1]

1911

1

T3

1

T11

1

T13

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	706	1			T13	7		T17	9		T18	4
read_ops[0x0b]	631	1			T13	6		T16	2		T17	6
read_ops[0x3b]	622	1			T11	2		T13	7		T17	7
read_ops[0x6b]	634	1			T13	11		T17	6		T18	1
read_ops[0xbb]	645	1			T13	9		T16	4		T17	7
read_ops[0xeb]	605	1			T3	2		T13	8		T17	10

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T19	3		T302	1		T65	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T17	1		T18	1		T33	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T35	1		T166	1		T19	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T166	1		T19	1		T187	3
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T36	1		T147	1		T32	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T17	1		T33	1		T36	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T198	1		T151	1		T120	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T36	1		T19	1		T149	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	249	1			T13	3		T17	3		T18	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T13	4		T17	4		T18	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T19	1		T20	1		T151	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	17	1			T167	1		T148	1		T309	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T13	1		T35	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T36	1		T167	1		T120	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T17	1		T35	1		T36	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T19	2		T149	1		T178	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T17	1		T19	2		T147	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T33	1		T19	1		T186	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	232	1			T13	2		T16	1		T17	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	234	1			T13	3		T16	1		T17	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T11	1		T35	1		T36	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T11	1		T13	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T17	1		T36	1		T19	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T13	1		T17	1		T36	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T35	2		T36	2		T20	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T35	2		T149	1		T20	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T167	1		T224	1		T196	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T33	1		T167	1		T32	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	231	1			T13	1		T17	2		T33	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	225	1			T13	4		T17	3		T33	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T19	1		T268	1		T20	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T13	1		T34	1		T35	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T13	1		T33	2		T19	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T19	2		T32	1		T154	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T19	1		T20	1		T120	3
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T18	1		T34	1		T35	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T13	1		T20	1		T154	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T33	1		T152	1		T212	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	238	1			T13	3		T33	6		T97	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	228	1			T13	5		T17	6		T33	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T18	1		T33	1		T268	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T13	1		T17	1		T35	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T35	2		T151	1		T148	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T13	1		T17	1		T19	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T13	1		T34	2		T36	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T17	1		T36	1		T149	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T35	1		T36	2		T167	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T13	1		T19	1		T151	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	227	1			T13	4		T16	2		T17	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	250	1			T13	1		T16	2		T17	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T13	1		T36	1		T149	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T34	1		T35	3		T36	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	13	1			T36	1		T32	1		T224	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T19	1		T151	1		T120	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T13	1		T17	1		T35	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T33	1		T187	1		T147	3
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T186	1		T154	1		T180	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T17	1		T271	1		T310	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	262	1			T3	1		T13	3		T17	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	189	1			T3	1		T13	3		T17	4