Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3186	1			T13	22		T17	20		T33	23
values[1]	3410	1			T17	41		T39	26		T33	20
values[2]	2979	1			T18	20		T33	20		T35	83
values[3]	3447	1			T3	8		T5	10		T13	65
values[4]	3459	1			T13	108		T30	2		T33	20
values[5]	3600	1			T11	2		T13	100		T16	20
values[6]	3420	1			T13	23		T17	161		T18	29
values[7]	3251	1			T33	24		T34	20		T146	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2838	1			T33	22		T35	26		T36	112
values[1]	3176	1			T3	8		T5	10		T16	20
values[2]	3992	1			T13	62		T17	64		T33	127
values[3]	2759	1			T17	20		T97	10		T35	50
values[4]	3095	1			T11	2		T13	60		T17	21
values[5]	3793	1			T13	40		T17	95		T30	2
values[6]	3621	1			T13	45		T17	90		T39	26
values[7]	3478	1			T13	111		T17	32		T18	29

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26135

1

T3

8

T5

10

T11

2

auto[1]

617

1

T13

9

T16

2

T17

8

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[3]]	[values[4]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	277	1			T19	31		T147	19		T148	19
auto[0]	values[0]	values[1]	214	1			T36	68		T149	20		T150	4
auto[0]	values[0]	values[2]	709	1			T13	21		T33	23		T36	20
auto[0]	values[0]	values[3]	319	1			T36	20		T40	16		T151	20
auto[0]	values[0]	values[4]	374	1			T19	18		T148	20		T152	20
auto[0]	values[0]	values[5]	366	1			T20	20		T153	4		T154	20
auto[0]	values[0]	values[6]	596	1			T17	20		T19	28		T147	180
auto[0]	values[0]	values[7]	257	1			T35	34		T155	37		T156	2
auto[0]	values[1]	values[0]	277	1			T35	25		T19	23		T120	24
auto[0]	values[1]	values[1]	428	1			T33	20		T34	25		T35	19
auto[0]	values[1]	values[2]	590	1			T17	19		T20	18		T81	8
auto[0]	values[1]	values[3]	214	1			T157	4		T158	20		T155	50
auto[0]	values[1]	values[4]	309	1			T17	21		T159	2		T160	12
auto[0]	values[1]	values[5]	465	1			T36	28		T19	20		T161	12
auto[0]	values[1]	values[6]	599	1			T39	26		T35	20		T36	97
auto[0]	values[1]	values[7]	456	1			T20	20		T162	18		T148	20
auto[0]	values[2]	values[0]	280	1			T36	20		T32	21		T154	19
auto[0]	values[2]	values[1]	497	1			T18	20		T151	45		T32	23
auto[0]	values[2]	values[2]	257	1			T148	18		T163	41		T53	10
auto[0]	values[2]	values[3]	396	1			T19	33		T164	20		T112	20
auto[0]	values[2]	values[4]	412	1			T35	46		T36	14		T19	29
auto[0]	values[2]	values[5]	411	1			T33	19		T35	34		T165	6
auto[0]	values[2]	values[6]	287	1			T166	2		T167	10		T32	26
auto[0]	values[2]	values[7]	367	1			T20	22		T168	12		T151	20
auto[0]	values[3]	values[0]	483	1			T33	19		T36	90		T19	20
auto[0]	values[3]	values[1]	361	1			T3	8		T5	10		T20	19
auto[0]	values[3]	values[2]	517	1			T36	67		T20	29		T169	10
auto[0]	values[3]	values[3]	339	1			T20	22		T170	4		T171	20
auto[0]	values[3]	values[4]	324	1			T172	8		T147	52		T173	10
auto[0]	values[3]	values[5]	481	1			T13	20		T17	19		T33	21
auto[0]	values[3]	values[6]	531	1			T17	25		T33	31		T36	20
auto[0]	values[3]	values[7]	330	1			T13	42		T17	32		T19	21
auto[0]	values[4]	values[0]	518	1			T174	8		T148	24		T44	24
auto[0]	values[4]	values[1]	345	1			T151	62		T147	23		T32	35
auto[0]	values[4]	values[2]	487	1			T13	20		T33	17		T148	20
auto[0]	values[4]	values[3]	408	1			T20	26		T175	14		T176	2
auto[0]	values[4]	values[4]	287	1			T13	22		T36	27		T19	85
auto[0]	values[4]	values[5]	624	1			T30	2		T34	20		T177	14
auto[0]	values[4]	values[6]	320	1			T19	21		T20	20		T178	20
auto[0]	values[4]	values[7]	389	1			T13	64		T179	22		T154	20
auto[0]	values[5]	values[0]	327	1			T149	20		T20	20		T180	20
auto[0]	values[5]	values[1]	382	1			T16	18		T35	20		T147	20
auto[0]	values[5]	values[2]	519	1			T13	18		T33	20		T181	177
auto[0]	values[5]	values[3]	444	1			T97	10		T35	24		T19	36
auto[0]	values[5]	values[4]	431	1			T11	2		T13	38		T35	36
auto[0]	values[5]	values[5]	454	1			T13	20		T182	34		T183	6
auto[0]	values[5]	values[6]	422	1			T13	21		T17	19		T19	55
auto[0]	values[5]	values[7]	542	1			T184	2		T185	2		T186	20
auto[0]	values[6]	values[0]	279	1			T187	14		T32	25		T139	27
auto[0]	values[6]	values[1]	591	1			T36	76		T19	20		T151	31
auto[0]	values[6]	values[2]	652	1			T17	43		T33	37		T34	93
auto[0]	values[6]	values[3]	250	1			T17	20		T188	14		T189	19
auto[0]	values[6]	values[4]	377	1			T19	30		T20	26		T190	4
auto[0]	values[6]	values[5]	368	1			T17	75		T19	20		T191	2
auto[0]	values[6]	values[6]	280	1			T13	23		T17	21		T33	20
auto[0]	values[6]	values[7]	544	1			T18	29		T33	23		T20	20
auto[0]	values[7]	values[0]	328	1			T192	6		T193	4		T189	83
auto[0]	values[7]	values[1]	288	1			T34	20		T149	20		T194	20
auto[0]	values[7]	values[2]	159	1			T33	23		T195	20		T196	40
auto[0]	values[7]	values[3]	334	1			T35	26		T83	8		T197	8
auto[0]	values[7]	values[4]	521	1			T198	10		T199	4		T186	32
auto[0]	values[7]	values[5]	538	1			T19	30		T20	25		T147	124
auto[0]	values[7]	values[6]	495	1			T19	23		T200	24		T152	54
auto[0]	values[7]	values[7]	509	1			T146	4		T201	49		T202	2
auto[1]	values[0]	values[0]	10	1			T19	1		T147	1		T148	1
auto[1]	values[0]	values[1]	4	1			T186	1		T32	1		T203	1
auto[1]	values[0]	values[2]	14	1			T13	1		T204	1		T205	2
auto[1]	values[0]	values[3]	10	1			T40	4		T206	2		T207	2
auto[1]	values[0]	values[4]	10	1			T19	3		T148	3		T208	1
auto[1]	values[0]	values[5]	7	1			T209	2		T210	2		T211	1
auto[1]	values[0]	values[6]	15	1			T19	1		T212	1		T213	1
auto[1]	values[0]	values[7]	4	1			T155	1		T214	1		T215	1
auto[1]	values[1]	values[0]	7	1			T35	1		T19	1		T120	1
auto[1]	values[1]	values[1]	11	1			T35	1		T186	1		T205	3
auto[1]	values[1]	values[2]	16	1			T17	1		T20	2		T189	1
auto[1]	values[1]	values[3]	6	1			T158	2		T155	2		T171	1
auto[1]	values[1]	values[4]	3	1			T216	3		-	-		-	-
auto[1]	values[1]	values[5]	9	1			T217	2		T195	5		T218	2
auto[1]	values[1]	values[6]	14	1			T36	3		T120	1		T148	1
auto[1]	values[1]	values[7]	6	1			T20	2		T155	1		T219	1
auto[1]	values[2]	values[0]	10	1			T32	1		T154	1		T205	4
auto[1]	values[2]	values[1]	12	1			T151	3		T220	1		T155	1
auto[1]	values[2]	values[2]	5	1			T148	3		T163	1		T214	1
auto[1]	values[2]	values[3]	10	1			T19	1		T221	3		T211	1
auto[1]	values[2]	values[4]	7	1			T36	6		T163	1		-	-
auto[1]	values[2]	values[5]	17	1			T33	1		T35	3		T189	2
auto[1]	values[2]	values[6]	5	1			T32	1		T155	1		T222	1
auto[1]	values[2]	values[7]	6	1			T20	1		T214	3		T223	2
auto[1]	values[3]	values[0]	12	1			T33	3		T36	2		T224	2
auto[1]	values[3]	values[1]	10	1			T20	2		T196	1		T225	4
auto[1]	values[3]	values[2]	14	1			T20	2		T226	3		T227	1
auto[1]	values[3]	values[3]	4	1			T20	2		T210	1		T228	1
auto[1]	values[3]	values[5]	8	1			T17	1		T229	2		T222	1
auto[1]	values[3]	values[6]	22	1			T17	3		T33	1		T120	5
auto[1]	values[3]	values[7]	11	1			T13	3		T171	4		T219	1
auto[1]	values[4]	values[0]	10	1			T230	1		T203	1		T231	2
auto[1]	values[4]	values[1]	8	1			T151	2		T32	3		T232	1
auto[1]	values[4]	values[2]	18	1			T33	3		T148	4		T224	2
auto[1]	values[4]	values[3]	8	1			T152	2		T180	4		T233	1
auto[1]	values[4]	values[4]	8	1			T36	1		T19	2		T41	2
auto[1]	values[4]	values[5]	14	1			T34	1		T32	1		T234	2
auto[1]	values[4]	values[6]	6	1			T180	1		T203	4		T223	1
auto[1]	values[4]	values[7]	9	1			T13	2		T212	2		T224	2
auto[1]	values[5]	values[0]	7	1			T171	2		T211	1		T216	4
auto[1]	values[5]	values[1]	6	1			T16	2		T155	1		T208	2
auto[1]	values[5]	values[2]	13	1			T13	2		T186	1		T154	5
auto[1]	values[5]	values[3]	3	1			T19	1		T235	1		T236	1
auto[1]	values[5]	values[4]	8	1			T19	2		T189	3		T210	1
auto[1]	values[5]	values[5]	8	1			T32	1		T180	2		T204	2
auto[1]	values[5]	values[6]	16	1			T13	1		T17	1		T19	3
auto[1]	values[5]	values[7]	18	1			T32	2		T158	5		T171	2
auto[1]	values[6]	values[0]	3	1			T227	2		T237	1		-	-
auto[1]	values[6]	values[1]	5	1			T148	2		T224	1		T219	1
auto[1]	values[6]	values[2]	19	1			T17	1		T33	3		T34	2
auto[1]	values[6]	values[3]	9	1			T189	1		T139	1		T238	4
auto[1]	values[6]	values[4]	10	1			T158	3		T222	2		T239	1
auto[1]	values[6]	values[5]	9	1			T180	3		T195	2		T234	2
auto[1]	values[6]	values[6]	6	1			T17	1		T228	3		T231	2
auto[1]	values[6]	values[7]	18	1			T33	2		T186	2		T158	1
auto[1]	values[7]	values[0]	10	1			T189	1		T195	5		T225	1
auto[1]	values[7]	values[1]	14	1			T120	2		T240	2		T241	4
auto[1]	values[7]	values[2]	3	1			T33	1		T216	2		-	-
auto[1]	values[7]	values[3]	5	1			T213	2		T242	2		T243	1
auto[1]	values[7]	values[4]	14	1			T120	2		T189	2		T229	1
auto[1]	values[7]	values[5]	14	1			T20	2		T147	3		T212	1
auto[1]	values[7]	values[6]	7	1			T19	2		T226	2		T232	1
auto[1]	values[7]	values[7]	12	1			T178	2		T234	1		T123	2