Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1647

1

T2

4

T4

14

T12

2

auto[1]

1616

1

T2

3

T4

18

T12

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1818

1

T2

7

T13

9

T14

9

auto[1]

1445

1

T4

32

T12

3

T13

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2563

1

T2

4

T4

32

T12

3

auto[1]

700

1

T2

3

T13

5

T14

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	706	1			T4	6		T12	1		T13	4
valid[1]	671	1			T2	3		T4	5		T13	2
valid[2]	643	1			T2	1		T4	5		T12	1
valid[3]	613	1			T2	1		T4	8		T13	1
valid[4]	630	1			T2	2		T4	8		T12	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	112	1			T18	3		T42	2		T19	3
auto[0]	auto[0]	valid[0]	auto[1]	166	1			T4	2		T12	1		T18	1
auto[0]	auto[0]	valid[1]	auto[0]	111	1			T17	2		T18	3		T42	3
auto[0]	auto[0]	valid[1]	auto[1]	159	1			T27	2		T333	2		T43	1
auto[0]	auto[0]	valid[2]	auto[0]	118	1			T15	3		T17	1		T18	4
auto[0]	auto[0]	valid[2]	auto[1]	140	1			T4	2		T12	1		T26	2
auto[0]	auto[0]	valid[3]	auto[0]	101	1			T13	1		T18	1		T33	1
auto[0]	auto[0]	valid[3]	auto[1]	147	1			T4	5		T26	4		T27	2
auto[0]	auto[0]	valid[4]	auto[0]	119	1			T2	1		T14	1		T17	2
auto[0]	auto[0]	valid[4]	auto[1]	139	1			T4	5		T18	1		T26	1
auto[0]	auto[1]	valid[0]	auto[0]	120	1			T13	2		T18	3		T42	1
auto[0]	auto[1]	valid[0]	auto[1]	152	1			T4	4		T14	1		T26	2
auto[0]	auto[1]	valid[1]	auto[0]	123	1			T2	1		T13	1		T14	1
auto[0]	auto[1]	valid[1]	auto[1]	131	1			T4	5		T26	1		T27	1
auto[0]	auto[1]	valid[2]	auto[0]	88	1			T18	2		T330	1		T19	1
auto[0]	auto[1]	valid[2]	auto[1]	154	1			T4	3		T26	2		T43	1
auto[0]	auto[1]	valid[3]	auto[0]	121	1			T2	1		T15	1		T18	5
auto[0]	auto[1]	valid[3]	auto[1]	125	1			T4	3		T26	1		T80	1
auto[0]	auto[1]	valid[4]	auto[0]	105	1			T2	1		T14	1		T17	3
auto[0]	auto[1]	valid[4]	auto[1]	132	1			T4	3		T12	1		T13	2
auto[1]	auto[0]	valid[0]	auto[0]	75	1			T13	1		T14	1		T18	4
auto[1]	auto[0]	valid[1]	auto[0]	76	1			T2	2		T15	1		T17	1
auto[1]	auto[0]	valid[2]	auto[0]	69	1			T2	1		T14	1		T18	1
auto[1]	auto[0]	valid[3]	auto[0]	55	1			T42	1		T19	2		T320	1
auto[1]	auto[0]	valid[4]	auto[0]	60	1			T13	1		T17	1		T142	1
auto[1]	auto[1]	valid[0]	auto[0]	81	1			T13	1		T15	1		T29	1
auto[1]	auto[1]	valid[1]	auto[0]	71	1			T13	1		T14	1		T15	1
auto[1]	auto[1]	valid[2]	auto[0]	74	1			T14	1		T18	1		T330	1
auto[1]	auto[1]	valid[3]	auto[0]	64	1			T33	1		T144	2		T145	3
auto[1]	auto[1]	valid[4]	auto[0]	75	1			T13	1		T14	2		T17	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal