Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	922	1			T14	11		T17	20		T19	7
all_values[1]	922	1			T14	11		T17	20		T19	7
all_values[2]	922	1			T14	11		T17	20		T19	7
all_values[3]	922	1			T14	11		T17	20		T19	7
all_values[4]	922	1			T14	11		T17	20		T19	7
all_values[5]	922	1			T14	11		T17	20		T19	7
all_values[6]	922	1			T14	11		T17	20		T19	7
all_values[7]	922	1			T14	11		T17	20		T19	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3944

1

T14

44

T17

83

T19

32

auto[1]

3432

1

T14

44

T17

77

T19

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2916

1

T14

32

T17

66

T19

19

auto[1]

4460

1

T14

56

T17

94

T19

37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4155

1

T14

49

T17

88

T19

34

auto[1]

3221

1

T14

39

T17

72

T19

22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	185	1			T17	2		T19	1		T21	2
all_values[0]	auto[0]	auto[0]	auto[1]	102	1			T17	3		T19	2		T127	2
all_values[0]	auto[0]	auto[1]	auto[0]	149	1			T14	3		T17	5		T127	1
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T14	3		T17	1		T19	1
all_values[0]	auto[1]	auto[0]	auto[1]	201	1			T14	3		T17	4		T19	2
all_values[0]	auto[1]	auto[1]	auto[1]	205	1			T14	2		T17	5		T19	1
all_values[1]	auto[0]	auto[0]	auto[0]	206	1			T14	3		T17	6		T19	2
all_values[1]	auto[0]	auto[0]	auto[1]	87	1			T17	1		T21	6		T22	1
all_values[1]	auto[0]	auto[1]	auto[0]	134	1			T14	2		T17	3		T19	1
all_values[1]	auto[0]	auto[1]	auto[1]	92	1			T14	1		T17	2		T19	2
all_values[1]	auto[1]	auto[0]	auto[1]	220	1			T14	3		T17	4		T19	1
all_values[1]	auto[1]	auto[1]	auto[1]	183	1			T14	2		T17	4		T19	1
all_values[2]	auto[0]	auto[0]	auto[0]	189	1			T14	1		T17	6		T19	3
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T14	2		T17	1		T21	2
all_values[2]	auto[0]	auto[1]	auto[0]	149	1			T17	4		T127	3		T23	4
all_values[2]	auto[0]	auto[1]	auto[1]	82	1			T14	1		T17	1		T19	1
all_values[2]	auto[1]	auto[0]	auto[1]	225	1			T14	1		T17	5		T19	1
all_values[2]	auto[1]	auto[1]	auto[1]	198	1			T14	6		T17	3		T19	2
all_values[3]	auto[0]	auto[0]	auto[0]	204	1			T14	5		T17	2		T21	1
all_values[3]	auto[0]	auto[0]	auto[1]	78	1			T17	3		T19	2		T127	1
all_values[3]	auto[0]	auto[1]	auto[0]	167	1			T14	3		T17	3		T127	1
all_values[3]	auto[0]	auto[1]	auto[1]	91	1			T17	1		T19	1		T21	4
all_values[3]	auto[1]	auto[0]	auto[1]	197	1			T14	1		T17	6		T19	3
all_values[3]	auto[1]	auto[1]	auto[1]	185	1			T14	2		T17	5		T19	1
all_values[4]	auto[0]	auto[0]	auto[0]	173	1			T14	1		T17	2		T19	1
all_values[4]	auto[0]	auto[0]	auto[1]	92	1			T14	1		T17	1		T19	2
all_values[4]	auto[0]	auto[1]	auto[0]	145	1			T14	2		T17	4		T19	1
all_values[4]	auto[0]	auto[1]	auto[1]	93	1			T14	2		T17	2		T127	2
all_values[4]	auto[1]	auto[0]	auto[1]	226	1			T14	3		T17	6		T19	2
all_values[4]	auto[1]	auto[1]	auto[1]	193	1			T14	2		T17	5		T19	1
all_values[5]	auto[0]	auto[0]	auto[0]	271	1			T14	3		T17	5		T19	1
all_values[5]	auto[0]	auto[1]	auto[0]	244	1			T14	4		T17	4		T19	4
all_values[5]	auto[1]	auto[0]	auto[1]	226	1			T14	3		T17	10		T19	1
all_values[5]	auto[1]	auto[1]	auto[1]	181	1			T14	1		T17	1		T19	1
all_values[6]	auto[0]	auto[0]	auto[0]	197	1			T14	2		T17	3		T19	2
all_values[6]	auto[0]	auto[0]	auto[1]	92	1			T14	3		T17	1		T19	1
all_values[6]	auto[0]	auto[1]	auto[0]	145	1			T14	2		T17	6		T19	1
all_values[6]	auto[0]	auto[1]	auto[1]	96	1			T17	3		T19	1		T127	2
all_values[6]	auto[1]	auto[0]	auto[1]	212	1			T14	4		T19	1		T21	4
all_values[6]	auto[1]	auto[1]	auto[1]	180	1			T17	7		T19	1		T127	2
all_values[7]	auto[0]	auto[0]	auto[0]	189	1			T17	7		T19	1		T21	5
all_values[7]	auto[0]	auto[0]	auto[1]	89	1			T14	1		T21	1		T22	1
all_values[7]	auto[0]	auto[1]	auto[0]	169	1			T14	1		T17	4		T19	1
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T14	3		T17	2		T19	2
all_values[7]	auto[1]	auto[0]	auto[1]	204	1			T14	4		T17	5		T19	3
all_values[7]	auto[1]	auto[1]	auto[1]	185	1			T14	2		T17	2		T22	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal