Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44987

1

T2

169

T10

1

T13

145

auto[1]

14681

1

T4

398

T12

3

T13

18

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43196

1

T2

116

T4

398

T10

1

auto[1]

16472

1

T2

53

T13

61

T14

74

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	30916	1			T2	88		T4	208		T10	1
others[1]	5138	1			T2	10		T4	39		T13	12
others[2]	4944	1			T2	17		T4	42		T13	12
others[3]	5589	1			T2	18		T4	34		T13	18
interest[1]	3256	1			T2	5		T4	22		T13	10
interest[4]	20252	1			T2	56		T4	139		T10	1
interest[64]	9825	1			T2	31		T4	53		T13	25

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14728	1			T2	64		T10	1		T13	44
auto[0]	auto[0]	others[1]	2464	1			T2	8		T13	7		T14	9
auto[0]	auto[0]	others[2]	2363	1			T2	12		T13	7		T14	8
auto[0]	auto[0]	others[3]	2686	1			T2	9		T13	10		T14	15
auto[0]	auto[0]	interest[1]	1593	1			T2	2		T13	4		T14	8
auto[0]	auto[0]	interest[4]	9559	1			T2	42		T10	1		T13	30
auto[0]	auto[0]	interest[64]	4681	1			T2	21		T13	12		T14	17
auto[0]	auto[1]	others[0]	7762	1			T4	208		T12	3		T13	8
auto[0]	auto[1]	others[1]	1269	1			T4	39		T13	1		T14	7
auto[0]	auto[1]	others[2]	1221	1			T4	42		T14	7		T15	2
auto[0]	auto[1]	others[3]	1347	1			T4	34		T13	2		T14	5
auto[0]	auto[1]	interest[1]	782	1			T4	22		T13	2		T14	6
auto[0]	auto[1]	interest[4]	5230	1			T4	139		T12	3		T13	4
auto[0]	auto[1]	interest[64]	2300	1			T4	53		T13	5		T14	4
auto[1]	auto[0]	others[0]	8426	1			T2	24		T13	34		T14	36
auto[1]	auto[0]	others[1]	1405	1			T2	2		T13	4		T14	5
auto[1]	auto[0]	others[2]	1360	1			T2	5		T13	5		T14	10
auto[1]	auto[0]	others[3]	1556	1			T2	9		T13	6		T14	6
auto[1]	auto[0]	interest[1]	881	1			T2	3		T13	4		T14	4
auto[1]	auto[0]	interest[4]	5463	1			T2	14		T13	19		T14	25
auto[1]	auto[0]	interest[64]	2844	1			T2	10		T13	8		T14	13

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal