Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2458489	1			T1	378		T2	233		T3	1
all_values[1]	2458489	1			T1	378		T2	233		T3	1
all_values[2]	2458489	1			T1	378		T2	233		T3	1
all_values[3]	2458489	1			T1	378		T2	233		T3	1
all_values[4]	2458489	1			T1	378		T2	233		T3	1
all_values[5]	2458489	1			T1	378		T2	233		T3	1
all_values[6]	2458489	1			T1	378		T2	233		T3	1
all_values[7]	2458489	1			T1	378		T2	233		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19254302

1

T1

3024

T2

1864

T3

8

auto[1]

413610

1

T37

36929

T13

28

T16

66

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19641104

1

T1

3024

T2

1864

T3

8

auto[1]

26808

1

T32

282

T35

186

T36

46

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2341395	1			T1	378		T2	233		T3	1
all_values[0]	auto[0]	auto[1]	11848	1			T32	120		T35	127		T36	39
all_values[0]	auto[1]	auto[0]	104259	1			T37	7293		T13	1		T16	3
all_values[0]	auto[1]	auto[1]	987	1			T37	90		T13	2		T16	2
all_values[1]	auto[0]	auto[0]	2412518	1			T1	378		T2	233		T3	1
all_values[1]	auto[0]	auto[1]	7896	1			T32	120		T35	56		T36	7
all_values[1]	auto[1]	auto[0]	37520	1			T37	7312		T13	4		T17	5
all_values[1]	auto[1]	auto[1]	555	1			T37	67		T16	5		T17	2
all_values[2]	auto[0]	auto[0]	2413722	1			T1	378		T2	233		T3	1
all_values[2]	auto[0]	auto[1]	3311	1			T32	42		T35	3		T37	43
all_values[2]	auto[1]	auto[0]	41059	1			T37	2		T13	6		T16	8
all_values[2]	auto[1]	auto[1]	397	1			T37	3		T13	2		T16	2
all_values[3]	auto[0]	auto[0]	2362711	1			T1	378		T2	233		T3	1
all_values[3]	auto[0]	auto[1]	211	1			T37	3		T13	2		T16	4
all_values[3]	auto[1]	auto[0]	95387	1			T37	7381		T13	3		T16	7
all_values[3]	auto[1]	auto[1]	180	1			T37	6		T13	1		T16	4
all_values[4]	auto[0]	auto[0]	2387398	1			T1	378		T2	233		T3	1
all_values[4]	auto[0]	auto[1]	200	1			T37	5		T13	2		T16	2
all_values[4]	auto[1]	auto[0]	70691	1			T37	2		T13	1		T16	7
all_values[4]	auto[1]	auto[1]	200	1			T37	3		T16	3		T17	3
all_values[5]	auto[0]	auto[0]	2432719	1			T1	378		T2	233		T3	1
all_values[5]	auto[0]	auto[1]	180	1			T37	4		T13	2		T16	2
all_values[5]	auto[1]	auto[0]	25436	1			T37	7377		T13	5		T16	10
all_values[5]	auto[1]	auto[1]	154	1			T37	1		T13	2		T16	2
all_values[6]	auto[0]	auto[0]	2431548	1			T1	378		T2	233		T3	1
all_values[6]	auto[0]	auto[1]	162	1			T13	3		T16	1		T17	2
all_values[6]	auto[1]	auto[0]	26613	1			T37	7381		T16	8		T17	6
all_values[6]	auto[1]	auto[1]	166	1			T13	1		T17	1		T18	5
all_values[7]	auto[0]	auto[0]	2448285	1			T1	378		T2	233		T3	1
all_values[7]	auto[0]	auto[1]	198	1			T37	2		T13	2		T16	7
all_values[7]	auto[1]	auto[0]	9843	1			T37	9		T16	3		T17	2
all_values[7]	auto[1]	auto[1]	163	1			T37	2		T16	2		T17	3