Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	31447	1			T1	257		T2	119		T5	4
auto[SpiFlashAddrCfg]	6414	1			T1	16		T2	8		T3	4
auto[SpiFlashAddr3b]	7765	1			T1	32		T2	9		T5	2
auto[SpiFlashAddr4b]	6505	1			T1	22		T2	9		T6	10

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29165

1

T1

104

T2

25

T3

4

auto[1]

22966

1

T1

223

T2

120

T8

10

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28336

1

T1

130

T2

123

T3

4

auto[1]

23795

1

T1

197

T2

22

T5

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	35347	1			T1	278		T2	128		T5	4
values[1]	921	1			T1	1		T2	3		T6	2
values[2]	1261	1			T1	2		T50	2		T39	2
values[3]	1294	1			T1	2		T2	3		T39	5
values[4]	1267	1			T1	3		T2	2		T5	2
values[5]	1225	1			T1	4		T7	2		T39	4
values[6]	1283	1			T1	5		T2	1		T6	2
values[7]	1217	1			T1	2		T3	4		T9	4
values[8]	8316	1			T1	30		T2	8		T6	10

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28540

1

T1

327

T3

4

T5

6

auto[1]

23591

1

T2

145

T7

4

T9

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

49490

1

T1

322

T2

138

T3

4

write

2641

1

T1

5

T2

7

T6

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16302

1

T1

51

T2

21

T3

4

valids[0x1]

35829

1

T1

276

T2

124

T5

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1241	1			T1	4		T2	2		T6	6
internal_process_ops[0x5a]	1299	1			T1	4		T2	3		T11	2
internal_process_ops[0x05]	19744	1			T1	231		T2	106		T39	169
internal_process_ops[0x35]	1348	1			T1	1		T8	2		T39	3
internal_process_ops[0x15]	1353	1			T1	4		T2	1		T5	4
internal_process_ops[0x03]	977	1			T1	8		T2	1		T7	1
internal_process_ops[0x0b]	897	1			T1	7		T9	4		T39	4
internal_process_ops[0x3b]	832	1			T1	5		T2	2		T6	2
internal_process_ops[0x6b]	935	1			T1	1		T5	2		T7	2
internal_process_ops[0xbb]	996	1			T1	5		T2	1		T6	6
internal_process_ops[0xeb]	923	1			T2	2		T3	4		T8	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50845

1

T1

325

T2

139

T3

4

auto[1]

1286

1

T1

2

T2

6

T11

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50277

1

T1

320

T2

138

T3

4

auto[1]

1854

1

T1

7

T2

7

T39

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9875

1

T1

66

T5

4

T6

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6429

1

T1

189

T8

2

T11

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1919

1

T1

10

T3

4

T6

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1502

1

T1

6

T8

2

T39

5

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2204

1

T1

17

T5

2

T6

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1914

1

T1

14

T8

6

T11

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1805

1

T1

9

T6

8

T50

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1538

1

T1

11

T39

7

T44

21

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

98

1

T1

1

T39

1

T44

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

89

1

T44

2

T27

5

T13

7

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

42

1

T1

1

T54

1

T173

7

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

89

1

T13

5

T53

2

T17

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

95

1

T43

8

T44

1

T13

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

90

1

T44

2

T52

1

T13

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

82

1

T44

1

T52

4

T13

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

73

1

T52

3

T13

2

T53

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

85

1

T39

1

T27

2

T13

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

59

1

T52

1

T13

4

T45

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

79

1

T44

1

T52

1

T13

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

107

1

T1

1

T11

2

T13

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

107

1

T1

1

T6

2

T44

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

88

1

T44

1

T27

4

T52

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

95

1

T39

3

T44

1

T13

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

76

1

T1

1

T52

2

T13

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8030

1

T2

10

T32

43

T35

173

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6445

1

T2

109

T32

23

T35

55

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1232

1

T2

2

T7

1

T9

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1121

1

T2

2

T32

7

T35

20

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1544

1

T2

5

T9

4

T10

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1445

1

T2

4

T32

1

T35

37

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1190

1

T2

4

T7

3

T32

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1297

1

T2

2

T32

12

T35

19

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

88

1

T36

4

T37

2

T38

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

80

1

T37

3

T14

5

T15

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

106

1

T32

2

T35

2

T37

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

76

1

T32

1

T14

3

T175

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

95

1

T32

2

T35

1

T38

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

80

1

T2

4

T32

2

T35

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

62

1

T14

2

T176

1

T84

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

63

1

T35

2

T37

2

T38

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

79

1

T32

2

T38

1

T175

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

75

1

T32

3

T38

1

T177

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

92

1

T37

3

T178

4

T175

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

82

1

T32

2

T35

1

T14

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

82

1

T32

1

T37

3

T38

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

76

1

T32

1

T37

2

T178

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

68

1

T2

1

T32

1

T35

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

83

1

T2

2

T35

5

T38

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3300	1			T1	19		T8	6		T51	8
auto[0]	values[0]	valids[0x1]	15516	1			T1	259		T5	4		T6	8
auto[0]	values[1]	valids[0x1]	462	1			T1	1		T6	2		T39	4
auto[0]	values[2]	valids[0x0]	518	1			T50	2		T39	2		T44	4
auto[0]	values[2]	valids[0x1]	239	1			T1	2		T44	1		T52	1
auto[0]	values[3]	valids[0x0]	493	1			T1	2		T39	5		T44	1
auto[0]	values[3]	valids[0x1]	268	1			T43	2		T44	7		T27	5
auto[0]	values[4]	valids[0x0]	461	1			T1	1		T5	2		T44	4
auto[0]	values[4]	valids[0x1]	270	1			T1	2		T39	1		T44	3
auto[0]	values[5]	valids[0x0]	435	1			T1	2		T39	2		T44	1
auto[0]	values[5]	valids[0x1]	273	1			T1	2		T39	2		T44	2
auto[0]	values[6]	valids[0x0]	447	1			T1	4		T6	2		T50	4
auto[0]	values[6]	valids[0x1]	291	1			T1	1		T44	3		T27	6
auto[0]	values[7]	valids[0x0]	478	1			T1	2		T3	4		T39	4
auto[0]	values[7]	valids[0x1]	254	1			T39	3		T44	2		T23	2
auto[0]	values[8]	valids[0x0]	3071	1			T1	21		T6	8		T8	2
auto[0]	values[8]	valids[0x1]	1764	1			T1	9		T6	2		T39	11
auto[1]	values[0]	valids[0x0]	3191	1			T2	11		T32	24		T35	48
auto[1]	values[0]	valids[0x1]	13340	1			T2	117		T7	1		T9	2
auto[1]	values[1]	valids[0x1]	459	1			T2	3		T32	5		T35	3
auto[1]	values[2]	valids[0x0]	304	1			T46	1		T32	1		T35	5
auto[1]	values[2]	valids[0x1]	200	1			T35	5		T36	3		T37	1
auto[1]	values[3]	valids[0x0]	323	1			T2	3		T32	2		T35	3
auto[1]	values[3]	valids[0x1]	210	1			T32	2		T35	4		T36	2
auto[1]	values[4]	valids[0x0]	341	1			T2	1		T7	1		T32	1
auto[1]	values[4]	valids[0x1]	195	1			T2	1		T35	5		T37	7
auto[1]	values[5]	valids[0x0]	321	1			T7	2		T32	1		T36	7
auto[1]	values[5]	valids[0x1]	196	1			T32	1		T35	2		T36	2
auto[1]	values[6]	valids[0x0]	326	1			T2	1		T35	1		T36	1
auto[1]	values[6]	valids[0x1]	219	1			T35	4		T36	1		T38	5
auto[1]	values[7]	valids[0x0]	280	1			T32	2		T35	1		T36	6
auto[1]	values[7]	valids[0x1]	205	1			T9	4		T35	5		T36	1
auto[1]	values[8]	valids[0x0]	2013	1			T2	5		T10	1		T32	12
auto[1]	values[8]	valids[0x1]	1468	1			T2	3		T32	8		T35	15