Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3032151

1

T1

2232

T2

285

T3

78

auto[1]

18380

1

T1

227

T2

105

T39

164

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

953653

1

T1

39

T2

25

T3

78

auto[1]

2096878

1

T1

2420

T2

365

T39

4571

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	547303	1			T1	348		T2	54		T3	33
auto[524288:1048575]	367491	1			T3	26		T7	53		T9	4575
auto[1048576:1572863]	354383	1			T5	6		T9	2		T10	4033
auto[1572864:2097151]	330751	1			T1	257		T5	26		T7	3
auto[2097152:2621439]	364524	1			T1	177		T2	69		T3	19
auto[2621440:3145727]	403279	1			T1	1298		T9	4		T50	546
auto[3145728:3670015]	345311	1			T1	379		T2	9		T5	130
auto[3670016:4194303]	337489	1			T2	258		T5	2		T7	88

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2117061

1

T1

2455

T2

387

T3

6

auto[1]

933470

1

T1

4

T2

3

T3

72

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2580858

1

T1

2133

T2

310

T3

78

auto[1]

469673

1

T1

326

T2

80

T51

10

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	180896	1			T1	8		T2	2		T3	33
auto[0]	auto[0]	auto[0:524287]	auto[1]	297930	1			T1	266		T2	2		T43	5740
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	94336	1			T3	26		T7	53		T9	4575
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	189126	1			T39	2		T32	1352		T44	3312
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	136514	1			T5	6		T9	2		T10	4033
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	174363	1			T39	256		T32	128		T44	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	115810	1			T5	26		T7	3		T9	306
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	164975	1			T32	3		T35	2746		T37	773
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	104492	1			T1	9		T3	19		T5	73
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	197571	1			T1	2		T32	1995		T35	897
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	108935	1			T1	4		T9	4		T50	546
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	230827	1			T1	1291		T39	333		T44	515
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	92534	1			T1	1		T2	1		T5	130
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	201018	1			T1	378		T39	256		T32	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	107462	1			T2	2		T5	2		T7	88
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	169717	1			T2	256		T39	2660		T32	515
auto[0]	auto[1]	auto[0:524287]	auto[0]	757	1			T2	3		T51	7		T35	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	64127	1			T44	384		T35	1		T36	631
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1272	1			T32	1		T44	13		T35	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	80333	1			T32	1		T44	10577		T35	257
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	4287	1			T39	3		T32	1		T35	9
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	37201	1			T39	257		T35	1173		T225	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	337	1			T1	1		T51	3		T35	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	48001	1			T1	256		T37	513		T13	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	689	1			T1	6		T2	8		T35	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	59789	1			T1	7		T2	4		T35	777
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	299	1			T1	3		T39	4		T44	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	60792	1			T39	128		T44	2869		T37	6
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1213	1			T2	2		T32	2		T44	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	48207	1			T2	5		T35	601		T37	769
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1964	1			T39	3		T35	5		T36	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	56377	1			T39	518		T35	513		T36	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	270	1			T1	3		T2	2		T43	8
auto[1]	auto[0]	auto[0:524287]	auto[1]	2623	1			T1	71		T2	45		T43	208
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	173	1			T32	1		T44	2		T35	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1689	1			T44	3		T35	31		T37	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	166	1			T44	3		T35	4		T37	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1270	1			T44	59		T35	7		T13	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	160	1			T32	3		T35	1		T37	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1104	1			T32	2		T35	5		T37	12
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	170	1			T1	2		T32	2		T35	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1404	1			T1	98		T32	4		T35	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	164	1			T35	2		T36	2		T37	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1656	1			T35	7		T37	5		T13	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	162	1			T44	2		T27	2		T13	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1788	1			T44	32		T27	42		T45	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	193	1			T32	3		T44	2		T38	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1360	1			T44	11		T38	2		T13	4
auto[1]	auto[1]	auto[0:524287]	auto[0]	53	1			T35	1		T14	3		T45	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	647	1			T35	36		T14	44		T45	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	52	1			T32	1		T44	2		T35	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	510	1			T32	1		T44	18		T35	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	63	1			T39	1		T35	1		T225	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	519	1			T39	53		T35	3		T175	15
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	34	1			T37	1		T13	3		T55	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	330	1			T37	15		T13	20		T55	7
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	54	1			T1	2		T2	4		T35	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	355	1			T1	51		T2	53		T35	23
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	55	1			T37	2		T38	1		T13	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	551	1			T37	72		T13	5		T176	41
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	44	1			T2	1		T27	1		T14	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	345	1			T27	20		T177	1		T176	5
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	43	1			T39	2		T35	1		T36	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	373	1			T39	108		T36	1		T13	34

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1641789	1			T1	1956		T2	263		T3	6
auto[0]	auto[0]	auto[1]	924717	1			T1	3		T3	72		T5	256
auto[0]	auto[1]	auto[0]	457210	1			T1	272		T2	21		T51	6
auto[0]	auto[1]	auto[1]	8435	1			T1	1		T2	1		T51	4
auto[1]	auto[0]	auto[0]	14107	1			T1	174		T2	46		T32	14
auto[1]	auto[0]	auto[1]	245	1			T2	1		T32	1		T43	1
auto[1]	auto[1]	auto[0]	3955	1			T1	53		T2	57		T39	164
auto[1]	auto[1]	auto[1]	73	1			T2	1		T44	1		T37	2