Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16514

1

T1

104

T3

4

T5

6

auto[1]

12026

1

T1

223

T8

10

T11

12

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3378	1			T51	8		T39	20		T44	53
values[1]	3836	1			T1	20		T44	82		T27	102
values[2]	3438	1			T1	70		T3	4		T11	12
values[3]	3521	1			T1	94		T57	4		T13	20
values[4]	3498	1			T44	20		T202	10		T52	25
values[5]	3431	1			T6	22		T23	10		T25	18
values[6]	3604	1			T1	70		T8	10		T39	20
values[7]	3834	1			T1	73		T5	6		T39	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3376	1			T3	4		T8	10		T27	20
values[1]	3008	1			T51	8		T44	20		T23	10
values[2]	3990	1			T43	234		T44	99		T25	18
values[3]	3153	1			T6	22		T11	12		T44	25
values[4]	3666	1			T1	73		T50	6		T57	4
values[5]	3732	1			T1	70		T5	6		T39	20
values[6]	3479	1			T1	164		T39	204		T44	136
values[7]	4136	1			T1	20		T39	40		T44	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	161	1			T45	15		T171	34		T173	20
auto[0]	values[0]	values[1]	387	1			T51	8		T44	14		T17	15
auto[0]	values[0]	values[2]	221	1			T209	15		T21	12		T218	8
auto[0]	values[0]	values[3]	107	1			T105	2		T173	12		T221	10
auto[0]	values[0]	values[4]	274	1			T173	44		T247	6		T248	12
auto[0]	values[0]	values[5]	206	1			T44	27		T218	12		T249	16
auto[0]	values[0]	values[6]	329	1			T58	6		T45	9		T18	15
auto[0]	values[0]	values[7]	203	1			T39	13		T13	9		T250	20
auto[0]	values[1]	values[0]	175	1			T27	8		T13	16		T191	13
auto[0]	values[1]	values[1]	188	1			T27	55		T53	14		T224	16
auto[0]	values[1]	values[2]	208	1			T13	11		T209	14		T216	12
auto[0]	values[1]	values[3]	308	1			T17	14		T173	13		T251	4
auto[0]	values[1]	values[4]	260	1			T27	14		T92	18		T226	10
auto[0]	values[1]	values[5]	294	1			T52	11		T106	6		T18	6
auto[0]	values[1]	values[6]	358	1			T44	72		T21	13		T199	19
auto[0]	values[1]	values[7]	323	1			T1	14		T45	25		T252	20
auto[0]	values[2]	values[0]	381	1			T3	4		T222	15		T200	13
auto[0]	values[2]	values[1]	236	1			T27	8		T13	23		T196	9
auto[0]	values[2]	values[2]	307	1			T13	18		T198	9		T199	11
auto[0]	values[2]	values[3]	203	1			T13	17		T208	11		T196	11
auto[0]	values[2]	values[4]	260	1			T50	6		T27	10		T54	16
auto[0]	values[2]	values[5]	188	1			T1	56		T39	12		T44	13
auto[0]	values[2]	values[6]	172	1			T39	14		T13	10		T173	37
auto[0]	values[2]	values[7]	272	1			T60	8		T54	7		T17	9
auto[0]	values[3]	values[0]	205	1			T53	7		T55	14		T209	16
auto[0]	values[3]	values[1]	453	1			T13	12		T55	18		T173	56
auto[0]	values[3]	values[2]	254	1			T54	14		T253	2		T17	14
auto[0]	values[3]	values[3]	375	1			T21	24		T218	78		T216	11
auto[0]	values[3]	values[4]	194	1			T57	4		T53	8		T173	8
auto[0]	values[3]	values[5]	198	1			T254	12		T219	10		T255	14
auto[0]	values[3]	values[6]	152	1			T1	13		T18	11		T256	2
auto[0]	values[3]	values[7]	357	1			T257	6		T55	18		T209	13
auto[0]	values[4]	values[0]	385	1			T13	13		T54	11		T55	18
auto[0]	values[4]	values[1]	110	1			T243	10		T217	13		T231	12
auto[0]	values[4]	values[2]	414	1			T52	13		T173	10		T222	35
auto[0]	values[4]	values[3]	119	1			T17	13		T217	23		T258	6
auto[0]	values[4]	values[4]	205	1			T45	10		T173	15		T196	9
auto[0]	values[4]	values[5]	232	1			T44	13		T202	10		T13	16
auto[0]	values[4]	values[6]	135	1			T53	9		T259	6		T243	14
auto[0]	values[4]	values[7]	369	1			T17	12		T18	15		T198	6
auto[0]	values[5]	values[0]	204	1			T13	14		T222	13		T195	26
auto[0]	values[5]	values[1]	233	1			T23	10		T45	15		T54	12
auto[0]	values[5]	values[2]	301	1			T25	18		T13	23		T226	15
auto[0]	values[5]	values[3]	362	1			T6	22		T27	122		T199	12
auto[0]	values[5]	values[4]	260	1			T226	29		T260	18		T231	10
auto[0]	values[5]	values[5]	261	1			T55	32		T226	15		T200	13
auto[0]	values[5]	values[6]	171	1			T27	50		T45	28		T18	11
auto[0]	values[5]	values[7]	283	1			T27	14		T197	12		T200	11
auto[0]	values[6]	values[0]	231	1			T52	24		T17	29		T261	4
auto[0]	values[6]	values[1]	146	1			T13	14		T45	17		T200	7
auto[0]	values[6]	values[2]	310	1			T44	89		T52	14		T209	8
auto[0]	values[6]	values[3]	178	1			T226	15		T198	13		T199	8
auto[0]	values[6]	values[4]	278	1			T44	10		T45	9		T173	6
auto[0]	values[6]	values[5]	258	1			T52	15		T208	8		T198	60
auto[0]	values[6]	values[6]	361	1			T1	14		T39	14		T44	14
auto[0]	values[6]	values[7]	241	1			T13	15		T55	14		T234	12
auto[0]	values[7]	values[0]	198	1			T17	4		T208	9		T262	6
auto[0]	values[7]	values[1]	283	1			T53	8		T45	12		T263	8
auto[0]	values[7]	values[2]	482	1			T43	234		T27	13		T171	10
auto[0]	values[7]	values[3]	191	1			T44	17		T13	15		T45	9
auto[0]	values[7]	values[4]	407	1			T1	7		T53	15		T264	2
auto[0]	values[7]	values[5]	274	1			T5	6		T44	6		T13	28
auto[0]	values[7]	values[6]	103	1			T234	8		T218	21		T216	8
auto[0]	values[7]	values[7]	320	1			T39	14		T44	12		T28	2
auto[1]	values[0]	values[0]	246	1			T45	5		T171	18		T173	149
auto[1]	values[0]	values[1]	141	1			T44	6		T17	5		T173	9
auto[1]	values[0]	values[2]	188	1			T209	5		T21	27		T218	12
auto[1]	values[0]	values[3]	148	1			T173	8		T221	12		T200	9
auto[1]	values[0]	values[4]	185	1			T173	9		T199	16		T201	7
auto[1]	values[0]	values[5]	226	1			T44	6		T218	81		T227	10
auto[1]	values[0]	values[6]	164	1			T45	13		T18	5		T200	35
auto[1]	values[0]	values[7]	192	1			T39	7		T13	11		T17	10
auto[1]	values[1]	values[0]	126	1			T27	12		T13	15		T191	7
auto[1]	values[1]	values[1]	141	1			T27	7		T53	24		T171	8
auto[1]	values[1]	values[2]	172	1			T13	10		T209	7		T216	8
auto[1]	values[1]	values[3]	303	1			T17	6		T173	7		T18	14
auto[1]	values[1]	values[4]	143	1			T27	6		T226	16		T203	10
auto[1]	values[1]	values[5]	449	1			T52	12		T18	14		T222	11
auto[1]	values[1]	values[6]	190	1			T44	10		T21	34		T199	5
auto[1]	values[1]	values[7]	198	1			T1	6		T45	16		T173	4
auto[1]	values[2]	values[0]	157	1			T222	27		T200	7		T201	7
auto[1]	values[2]	values[1]	139	1			T27	12		T13	48		T196	37
auto[1]	values[2]	values[2]	231	1			T13	25		T198	92		T199	10
auto[1]	values[2]	values[3]	186	1			T11	12		T13	3		T208	9
auto[1]	values[2]	values[4]	146	1			T27	24		T54	9		T191	13
auto[1]	values[2]	values[5]	91	1			T1	14		T39	8		T44	7
auto[1]	values[2]	values[6]	391	1			T39	170		T13	11		T173	7
auto[1]	values[2]	values[7]	78	1			T60	12		T54	13		T17	11
auto[1]	values[3]	values[0]	112	1			T53	18		T55	6		T209	14
auto[1]	values[3]	values[1]	203	1			T13	8		T55	10		T173	6
auto[1]	values[3]	values[2]	181	1			T54	6		T17	17		T265	14
auto[1]	values[3]	values[3]	132	1			T21	6		T266	10		T218	9
auto[1]	values[3]	values[4]	248	1			T53	12		T173	12		T267	24
auto[1]	values[3]	values[5]	77	1			T254	8		T268	2		T255	10
auto[1]	values[3]	values[6]	155	1			T1	81		T18	9		T198	10
auto[1]	values[3]	values[7]	225	1			T55	6		T209	7		T198	21
auto[1]	values[4]	values[0]	236	1			T13	7		T54	9		T55	24
auto[1]	values[4]	values[1]	64	1			T243	10		T217	7		T231	8
auto[1]	values[4]	values[2]	202	1			T52	12		T173	10		T222	6
auto[1]	values[4]	values[3]	64	1			T17	9		T217	3		T163	18
auto[1]	values[4]	values[4]	140	1			T45	10		T56	8		T173	5
auto[1]	values[4]	values[5]	196	1			T44	7		T13	7		T209	13
auto[1]	values[4]	values[6]	220	1			T53	58		T243	9		T236	18
auto[1]	values[4]	values[7]	407	1			T17	19		T18	5		T198	76
auto[1]	values[5]	values[0]	157	1			T13	9		T222	7		T269	14
auto[1]	values[5]	values[1]	54	1			T45	13		T54	14		T231	8
auto[1]	values[5]	values[2]	304	1			T13	45		T226	7		T198	11
auto[1]	values[5]	values[3]	96	1			T27	7		T199	8		T218	11
auto[1]	values[5]	values[4]	197	1			T226	10		T220	12		T231	10
auto[1]	values[5]	values[5]	147	1			T55	3		T226	10		T200	35
auto[1]	values[5]	values[6]	157	1			T27	13		T45	21		T18	9
auto[1]	values[5]	values[7]	244	1			T27	6		T200	9		T199	4
auto[1]	values[6]	values[0]	140	1			T8	10		T52	22		T17	17
auto[1]	values[6]	values[1]	56	1			T13	6		T45	3		T200	13
auto[1]	values[6]	values[2]	92	1			T44	10		T52	9		T209	12
auto[1]	values[6]	values[3]	273	1			T226	18		T198	7		T199	14
auto[1]	values[6]	values[4]	176	1			T44	10		T45	15		T173	14
auto[1]	values[6]	values[5]	521	1			T52	13		T208	170		T198	4
auto[1]	values[6]	values[6]	181	1			T1	56		T39	6		T44	40
auto[1]	values[6]	values[7]	162	1			T13	5		T141	20		T55	6
auto[1]	values[7]	values[0]	262	1			T17	16		T208	148		T203	11
auto[1]	values[7]	values[1]	174	1			T53	12		T45	16		T222	22
auto[1]	values[7]	values[2]	123	1			T27	7		T171	10		T222	4
auto[1]	values[7]	values[3]	108	1			T44	8		T13	13		T45	11
auto[1]	values[7]	values[4]	293	1			T1	66		T53	5		T18	8
auto[1]	values[7]	values[5]	114	1			T44	14		T13	18		T21	7
auto[1]	values[7]	values[6]	240	1			T234	36		T218	98		T216	28
auto[1]	values[7]	values[7]	262	1			T39	6		T44	8		T13	10