Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2458489	1			T1	378		T2	233		T3	1
all_pins[1]	2458489	1			T1	378		T2	233		T3	1
all_pins[2]	2458489	1			T1	378		T2	233		T3	1
all_pins[3]	2458489	1			T1	378		T2	233		T3	1
all_pins[4]	2458489	1			T1	378		T2	233		T3	1
all_pins[5]	2458489	1			T1	378		T2	233		T3	1
all_pins[6]	2458489	1			T1	378		T2	233		T3	1
all_pins[7]	2458489	1			T1	378		T2	233		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19637252	1			T1	3024		T2	1864		T3	8
values[0x1]	30660	1			T37	7778		T13	8		T16	20
transitions[0x0=>0x1]	28729	1			T37	7477		T13	8		T16	17
transitions[0x1=>0x0]	28741	1			T37	7477		T13	8		T16	17

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2457393	1			T1	378		T2	233		T3	1
all_pins[0]	values[0x1]	1096	1			T37	102		T13	2		T16	2
all_pins[0]	transitions[0x0=>0x1]	716	1			T37	25		T13	2		T17	2
all_pins[0]	transitions[0x1=>0x0]	227	1			T16	3		T18	4		T19	1
all_pins[1]	values[0x0]	2457882	1			T1	378		T2	233		T3	1
all_pins[1]	values[0x1]	607	1			T37	77		T16	5		T17	2
all_pins[1]	transitions[0x0=>0x1]	482	1			T37	77		T16	5		T17	2
all_pins[1]	transitions[0x1=>0x0]	288	1			T37	3		T13	2		T16	2
all_pins[2]	values[0x0]	2458076	1			T1	378		T2	233		T3	1
all_pins[2]	values[0x1]	413	1			T37	3		T13	2		T16	2
all_pins[2]	transitions[0x0=>0x1]	360	1			T37	1		T13	2		T16	1
all_pins[2]	transitions[0x1=>0x0]	127	1			T37	4		T13	1		T16	3
all_pins[3]	values[0x0]	2458309	1			T1	378		T2	233		T3	1
all_pins[3]	values[0x1]	180	1			T37	6		T13	1		T16	4
all_pins[3]	transitions[0x0=>0x1]	131	1			T37	6		T13	1		T16	4
all_pins[3]	transitions[0x1=>0x0]	151	1			T37	3		T16	3		T17	2
all_pins[4]	values[0x0]	2458289	1			T1	378		T2	233		T3	1
all_pins[4]	values[0x1]	200	1			T37	3		T16	3		T17	3
all_pins[4]	transitions[0x0=>0x1]	164	1			T37	3		T16	3		T17	1
all_pins[4]	transitions[0x1=>0x0]	1550	1			T37	224		T13	2		T16	2
all_pins[5]	values[0x0]	2456903	1			T1	378		T2	233		T3	1
all_pins[5]	values[0x1]	1586	1			T37	224		T13	2		T16	2
all_pins[5]	transitions[0x0=>0x1]	391	1			T37	3		T13	2		T16	2
all_pins[5]	transitions[0x1=>0x0]	25220	1			T37	7140		T13	1		T18	3
all_pins[6]	values[0x0]	2432074	1			T1	378		T2	233		T3	1
all_pins[6]	values[0x1]	26415	1			T37	7361		T13	1		T17	1
all_pins[6]	transitions[0x0=>0x1]	26373	1			T37	7361		T13	1		T17	1
all_pins[6]	transitions[0x1=>0x0]	121	1			T37	2		T16	2		T17	3
all_pins[7]	values[0x0]	2458326	1			T1	378		T2	233		T3	1
all_pins[7]	values[0x1]	163	1			T37	2		T16	2		T17	3
all_pins[7]	transitions[0x0=>0x1]	112	1			T37	1		T16	2		T17	3
all_pins[7]	transitions[0x1=>0x0]	1057	1			T37	101		T13	2		T16	2