Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	322	1			T1	3		T39	3		T44	1
auto[ReadAddrCrossIntoMailbox]	266	1			T39	3		T44	7		T52	5
auto[ReadAddrCrossOutOfMailbox]	259	1			T1	2		T50	2		T39	3
auto[ReadAddrCrossAllMailbox]	187	1			T50	4		T39	2		T44	2
auto[ReadAddrOutsideMailbox]	3133	1			T1	21		T3	4		T5	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2093

1

T1

6

T3

2

T5

1

auto[1]

2074

1

T1

20

T3

2

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	741	1			T1	8		T39	6		T44	4
read_ops[0x0b]	651	1			T1	7		T39	4		T43	2
read_ops[0x3b]	631	1			T1	5		T6	2		T39	1
read_ops[0x6b]	705	1			T1	1		T5	2		T50	2
read_ops[0xbb]	760	1			T1	5		T6	6		T50	4
read_ops[0xeb]	679	1			T3	4		T8	2		T39	3

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T53	1		T106	1		T17	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T39	1		T52	1		T60	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T39	1		T45	2		T224	3
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T45	1		T224	3		T173	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T1	1		T45	1		T17	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T13	1		T45	2		T226	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T106	1		T199	1		T230	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T106	1		T45	1		T55	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T39	1		T44	1		T25	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T1	7		T39	3		T44	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T53	1		T45	1		T173	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T1	1		T39	1		T27	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T60	1		T173	2		T200	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T44	2		T52	1		T221	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T27	1		T45	1		T17	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T39	1		T27	1		T18	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T13	1		T53	1		T17	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T39	1		T194	1		T61	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	265	1			T1	3		T39	1		T43	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	245	1			T1	3		T43	1		T44	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T55	1		T172	1		T221	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	17	1			T1	2		T172	1		T222	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T13	2		T53	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T60	1		T55	1		T18	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T13	1		T17	1		T173	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T39	1		T17	2		T234	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T198	1		T271	1		T217	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T18	2		T209	1		T271	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	253	1			T6	1		T44	2		T58	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	226	1			T1	3		T6	1		T44	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T27	1		T13	1		T54	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T27	1		T53	2		T45	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T39	1		T44	1		T13	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T52	1		T45	1		T224	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T224	1		T226	1		T230	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T39	1		T13	1		T224	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T50	1		T39	1		T13	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T50	1		T44	1		T27	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	301	1			T5	1		T44	6		T202	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	216	1			T1	1		T5	1		T39	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T53	1		T54	2		T171	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T27	1		T53	1		T45	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	11	1			T55	2		T209	1		T222	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T39	1		T44	1		T13	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T50	1		T44	1		T53	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T1	1		T50	1		T45	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T50	1		T198	1		T230	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T50	1		T27	1		T45	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	282	1			T1	2		T6	3		T44	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T1	2		T6	3		T44	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T60	1		T45	1		T172	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T39	1		T44	1		T27	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T44	3		T52	3		T216	4
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T17	1		T209	1		T199	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T13	1		T45	1		T223	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T55	1		T171	1		T226	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T52	2		T13	1		T234	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T44	1		T27	1		T198	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	250	1			T3	2		T8	1		T44	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	259	1			T3	2		T8	1		T39	2