Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4123	1			T1	20		T51	8		T43	234
values[1]	3989	1			T8	10		T11	12		T27	62
values[2]	3137	1			T1	73		T44	85		T58	6
values[3]	3309	1			T1	70		T3	4		T39	20
values[4]	3614	1			T44	20		T202	10		T23	10
values[5]	3629	1			T6	22		T44	214		T27	151
values[6]	3094	1			T1	70		T5	6		T50	6
values[7]	3645	1			T1	94		T39	224		T25	18

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3812	1			T1	163		T43	234		T27	20
values[1]	3907	1			T3	4		T5	6		T57	4
values[2]	3204	1			T51	8		T39	20		T44	102
values[3]	3785	1			T1	94		T39	20		T44	20
values[4]	4209	1			T11	12		T39	204		T25	18
values[5]	3153	1			T44	94		T52	48		T13	64
values[6]	2922	1			T6	22		T44	99		T105	2
values[7]	3548	1			T1	70		T8	10		T50	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27869

1

T1

325

T3

4

T5

6

auto[1]

671

1

T1

2

T11

2

T44

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	699	1			T1	20		T43	234		T139	10
auto[0]	values[0]	values[1]	548	1			T203	86		T201	19		T194	102
auto[0]	values[0]	values[2]	342	1			T51	8		T13	20		T55	20
auto[0]	values[0]	values[3]	732	1			T52	28		T234	44		T21	69
auto[0]	values[0]	values[4]	325	1			T45	20		T173	20		T272	14
auto[0]	values[0]	values[5]	351	1			T44	20		T13	23		T273	6
auto[0]	values[0]	values[6]	355	1			T105	2		T173	20		T198	16
auto[0]	values[0]	values[7]	674	1			T44	20		T54	20		T264	2
auto[0]	values[1]	values[0]	513	1			T106	6		T45	20		T221	20
auto[0]	values[1]	values[1]	462	1			T45	20		T172	10		T200	20
auto[0]	values[1]	values[2]	410	1			T27	62		T45	20		T173	97
auto[0]	values[1]	values[3]	558	1			T52	20		T53	44		T54	25
auto[0]	values[1]	values[4]	815	1			T11	10		T55	32		T56	6
auto[0]	values[1]	values[5]	261	1			T52	24		T252	20		T208	20
auto[0]	values[1]	values[6]	324	1			T13	20		T17	22		T274	4
auto[0]	values[1]	values[7]	557	1			T8	10		T173	44		T234	60
auto[0]	values[2]	values[0]	318	1			T1	71		T275	10		T94	8
auto[0]	values[2]	values[1]	578	1			T44	44		T209	20		T198	82
auto[0]	values[2]	values[2]	237	1			T13	20		T224	16		T198	20
auto[0]	values[2]	values[3]	375	1			T44	20		T58	6		T197	12
auto[0]	values[2]	values[4]	542	1			T13	43		T45	22		T55	22
auto[0]	values[2]	values[5]	296	1			T44	20		T257	6		T250	20
auto[0]	values[2]	values[6]	374	1			T256	2		T200	68		T199	48
auto[0]	values[2]	values[7]	334	1			T13	64		T171	22		T173	71
auto[0]	values[3]	values[0]	392	1			T1	70		T13	21		T173	20
auto[0]	values[3]	values[1]	437	1			T3	4		T57	4		T27	18
auto[0]	values[3]	values[2]	455	1			T253	2		T198	20		T200	27
auto[0]	values[3]	values[3]	476	1			T60	20		T13	18		T54	20
auto[0]	values[3]	values[4]	275	1			T39	20		T27	39		T45	21
auto[0]	values[3]	values[5]	350	1			T17	20		T200	20		T199	20
auto[0]	values[3]	values[6]	441	1			T45	26		T92	18		T54	26
auto[0]	values[3]	values[7]	407	1			T260	18		T216	23		T194	34
auto[0]	values[4]	values[0]	365	1			T52	18		T141	20		T53	65
auto[0]	values[4]	values[1]	438	1			T23	10		T27	34		T53	37
auto[0]	values[4]	values[2]	533	1			T44	20		T27	19		T18	18
auto[0]	values[4]	values[3]	321	1			T202	10		T27	20		T13	20
auto[0]	values[4]	values[4]	346	1			T54	20		T55	21		T17	20
auto[0]	values[4]	values[5]	908	1			T13	20		T17	25		T251	4
auto[0]	values[4]	values[6]	383	1			T13	22		T234	54		T222	34
auto[0]	values[4]	values[7]	247	1			T18	20		T276	20		T245	27
auto[0]	values[5]	values[0]	548	1			T52	22		T13	62		T266	8
auto[0]	values[5]	values[1]	466	1			T44	31		T198	64		T196	20
auto[0]	values[5]	values[2]	474	1			T44	80		T27	126		T171	45
auto[0]	values[5]	values[3]	310	1			T13	27		T173	47		T199	18
auto[0]	values[5]	values[4]	670	1			T28	2		T263	8		T18	20
auto[0]	values[5]	values[5]	259	1			T277	4		T216	23		T203	25
auto[0]	values[5]	values[6]	355	1			T6	22		T44	99		T27	22
auto[0]	values[5]	values[7]	449	1			T55	20		T17	31		T278	12
auto[0]	values[6]	values[0]	412	1			T27	20		T173	20		T279	20
auto[0]	values[6]	values[1]	358	1			T5	6		T280	16		T261	4
auto[0]	values[6]	values[2]	367	1			T39	20		T53	20		T17	30
auto[0]	values[6]	values[3]	557	1			T226	24		T198	20		T240	8
auto[0]	values[6]	values[4]	591	1			T13	48		T53	17		T45	20
auto[0]	values[6]	values[5]	208	1			T44	54		T13	17		T209	20
auto[0]	values[6]	values[6]	173	1			T173	20		T200	18		T228	18
auto[0]	values[6]	values[7]	350	1			T1	70		T50	6		T17	20
auto[0]	values[7]	values[0]	454	1			T196	54		T281	16		T282	14
auto[0]	values[7]	values[1]	533	1			T45	24		T173	101		T200	18
auto[0]	values[7]	values[2]	316	1			T13	21		T174	4		T283	32
auto[0]	values[7]	values[3]	360	1			T1	94		T39	20		T230	111
auto[0]	values[7]	values[4]	552	1			T39	184		T25	18		T45	20
auto[0]	values[7]	values[5]	454	1			T52	23		T45	28		T54	19
auto[0]	values[7]	values[6]	436	1			T27	19		T45	28		T284	40
auto[0]	values[7]	values[7]	463	1			T39	20		T222	41		T213	22
auto[1]	values[0]	values[0]	14	1			T246	3		T245	2		T285	2
auto[1]	values[0]	values[1]	18	1			T201	1		T194	1		T210	4
auto[1]	values[0]	values[2]	9	1			T222	1		T286	3		T287	2
auto[1]	values[0]	values[3]	20	1			T198	3		T199	1		T218	6
auto[1]	values[0]	values[4]	2	1			T288	1		T289	1		-	-
auto[1]	values[0]	values[5]	8	1			T236	1		T210	1		T61	3
auto[1]	values[0]	values[6]	13	1			T198	4		T216	2		T201	2
auto[1]	values[0]	values[7]	13	1			T203	3		T210	1		T204	1
auto[1]	values[1]	values[0]	11	1			T196	1		T216	5		T61	2
auto[1]	values[1]	values[1]	14	1			T196	1		T203	1		T245	1
auto[1]	values[1]	values[2]	7	1			T173	1		T210	2		T290	2
auto[1]	values[1]	values[3]	14	1			T52	3		T53	1		T208	5
auto[1]	values[1]	values[4]	25	1			T11	2		T55	3		T56	2
auto[1]	values[1]	values[5]	6	1			T52	1		T226	2		T146	1
auto[1]	values[1]	values[6]	5	1			T267	2		T191	2		T201	1
auto[1]	values[1]	values[7]	7	1			T291	2		T292	1		T289	1
auto[1]	values[2]	values[0]	14	1			T1	2		T210	3		T285	4
auto[1]	values[2]	values[1]	11	1			T44	1		T218	3		T293	1
auto[1]	values[2]	values[2]	5	1			T13	1		T290	1		T294	1
auto[1]	values[2]	values[3]	5	1			T18	4		T295	1		-	-
auto[1]	values[2]	values[4]	18	1			T13	2		T203	2		T246	2
auto[1]	values[2]	values[5]	8	1			T254	1		T163	4		T290	3
auto[1]	values[2]	values[6]	13	1			T200	1		T61	3		T296	1
auto[1]	values[2]	values[7]	9	1			T13	5		T171	1		T217	1
auto[1]	values[3]	values[0]	5	1			T13	2		T231	2		T297	1
auto[1]	values[3]	values[1]	10	1			T27	2		T13	1		T236	2
auto[1]	values[3]	values[2]	13	1			T210	2		T294	3		T298	1
auto[1]	values[3]	values[3]	9	1			T13	2		T171	1		T209	1
auto[1]	values[3]	values[4]	8	1			T27	2		T230	1		T286	3
auto[1]	values[3]	values[5]	6	1			T210	1		T97	3		T296	1
auto[1]	values[3]	values[6]	14	1			T45	3		T217	2		T254	1
auto[1]	values[3]	values[7]	11	1			T288	2		T299	2		T294	1
auto[1]	values[4]	values[0]	11	1			T52	2		T53	2		T173	2
auto[1]	values[4]	values[1]	10	1			T53	1		T209	4		T286	2
auto[1]	values[4]	values[2]	10	1			T27	1		T18	2		T289	2
auto[1]	values[4]	values[3]	7	1			T55	1		T222	3		T300	1
auto[1]	values[4]	values[4]	7	1			T222	2		T199	1		T236	1
auto[1]	values[4]	values[5]	14	1			T17	1		T226	4		T198	1
auto[1]	values[4]	values[6]	11	1			T13	1		T234	2		T301	2
auto[1]	values[4]	values[7]	3	1			T245	1		T302	1		T303	1
auto[1]	values[5]	values[0]	26	1			T52	4		T13	5		T266	2
auto[1]	values[5]	values[1]	6	1			T44	2		T218	4		-	-
auto[1]	values[5]	values[2]	12	1			T44	2		T27	3		T171	1
auto[1]	values[5]	values[3]	17	1			T13	4		T173	1		T199	2
auto[1]	values[5]	values[4]	8	1			T208	3		T199	1		T236	1
auto[1]	values[5]	values[5]	7	1			T231	1		T304	1		T301	3
auto[1]	values[5]	values[6]	9	1			T191	3		T231	1		T194	2
auto[1]	values[5]	values[7]	13	1			T305	2		T296	2		T306	1
auto[1]	values[6]	values[0]	16	1			T200	3		T243	1		T191	1
auto[1]	values[6]	values[1]	11	1			T61	5		T296	2		T298	1
auto[1]	values[6]	values[2]	8	1			T17	1		T21	2		T303	1
auto[1]	values[6]	values[3]	17	1			T226	2		T199	1		T290	2
auto[1]	values[6]	values[4]	14	1			T53	3		T173	1		T198	1
auto[1]	values[6]	values[5]	6	1			T13	4		T307	2		-	-
auto[1]	values[6]	values[6]	4	1			T200	2		T201	1		T290	1
auto[1]	values[6]	values[7]	2	1			T61	2		-	-		-	-
auto[1]	values[7]	values[0]	14	1			T282	2		T236	1		T216	1
auto[1]	values[7]	values[1]	7	1			T173	1		T200	2		T288	1
auto[1]	values[7]	values[2]	6	1			T216	2		T163	1		T69	1
auto[1]	values[7]	values[3]	7	1			T230	3		T61	2		T166	2
auto[1]	values[7]	values[4]	11	1			T230	3		T201	1		T289	2
auto[1]	values[7]	values[5]	11	1			T54	1		T55	3		T221	1
auto[1]	values[7]	values[6]	12	1			T27	1		T198	1		T243	2
auto[1]	values[7]	values[7]	9	1			T199	2		T230	2		T243	1