| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 8 | 0 | 8 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_flip_position | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
| cp_opcode | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 103 | 1 | T7 | 1 | T9 | 1 | T46 | 1 | ||||
| auto[1] | 32 | 1 | T239 | 2 | T308 | 1 | T309 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| read_ops[0x03] | 19 | 1 | T7 | 1 | T308 | 6 | T310 | 4 | ||||
| read_ops[0x0b] | 15 | 1 | T9 | 1 | T46 | 1 | T311 | 2 | ||||
| read_ops[0x3b] | 34 | 1 | T312 | 4 | T313 | 10 | T314 | 10 | ||||
| read_ops[0x6b] | 23 | 1 | T309 | 3 | T315 | 1 | T316 | 4 | ||||
| read_ops[0xbb] | 15 | 1 | T317 | 1 | T318 | 2 | T319 | 3 | ||||
| read_ops[0xeb] | 29 | 1 | T239 | 10 | T317 | 1 | T318 | 12 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |