Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1683

1

T32

8

T33

15

T34

2

auto[1]

1770

1

T32

13

T33

14

T34

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1892

1

T32

21

T35

5

T36

7

auto[1]

1561

1

T33

29

T34

5

T35

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2679

1

T32

13

T33

29

T34

5

auto[1]

774

1

T32

8

T35

3

T36

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	725	1			T32	3		T33	6		T34	1
valid[1]	684	1			T32	7		T33	7		T34	1
valid[2]	692	1			T32	3		T33	8		T34	1
valid[3]	661	1			T32	5		T33	4		T34	1
valid[4]	691	1			T32	3		T33	4		T34	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	119	1			T32	1		T36	1		T37	2
auto[0]	auto[0]	valid[0]	auto[1]	161	1			T33	2		T35	2		T29	1
auto[0]	auto[0]	valid[1]	auto[0]	102	1			T32	2		T29	3		T13	2
auto[0]	auto[0]	valid[1]	auto[1]	136	1			T33	3		T52	1		T335	3
auto[0]	auto[0]	valid[2]	auto[0]	86	1			T32	1		T29	1		T60	2
auto[0]	auto[0]	valid[2]	auto[1]	168	1			T33	5		T34	1		T52	1
auto[0]	auto[0]	valid[3]	auto[0]	114	1			T32	1		T37	1		T52	1
auto[0]	auto[0]	valid[3]	auto[1]	147	1			T33	3		T34	1		T35	1
auto[0]	auto[0]	valid[4]	auto[0]	121	1			T32	1		T35	1		T36	1
auto[0]	auto[0]	valid[4]	auto[1]	138	1			T33	2		T35	1		T91	1
auto[0]	auto[1]	valid[0]	auto[0]	114	1			T32	1		T38	1		T60	1
auto[0]	auto[1]	valid[0]	auto[1]	158	1			T33	4		T34	1		T35	2
auto[0]	auto[1]	valid[1]	auto[0]	120	1			T32	3		T37	1		T29	1
auto[0]	auto[1]	valid[1]	auto[1]	163	1			T33	4		T34	1		T52	1
auto[0]	auto[1]	valid[2]	auto[0]	117	1			T36	1		T29	2		T55	1
auto[0]	auto[1]	valid[2]	auto[1]	159	1			T33	3		T35	1		T38	1
auto[0]	auto[1]	valid[3]	auto[0]	104	1			T32	3		T37	1		T52	2
auto[0]	auto[1]	valid[3]	auto[1]	156	1			T33	1		T35	1		T52	2
auto[0]	auto[1]	valid[4]	auto[0]	121	1			T35	1		T29	1		T60	1
auto[0]	auto[1]	valid[4]	auto[1]	175	1			T33	2		T34	1		T35	1
auto[1]	auto[0]	valid[0]	auto[0]	89	1			T52	1		T60	1		T14	1
auto[1]	auto[0]	valid[1]	auto[0]	80	1			T32	1		T36	2		T37	1
auto[1]	auto[0]	valid[2]	auto[0]	82	1			T32	1		T35	1		T52	1
auto[1]	auto[0]	valid[3]	auto[0]	75	1			T13	1		T14	1		T137	1
auto[1]	auto[0]	valid[4]	auto[0]	65	1			T52	1		T60	1		T13	2
auto[1]	auto[1]	valid[0]	auto[0]	84	1			T32	1		T37	1		T38	1
auto[1]	auto[1]	valid[1]	auto[0]	83	1			T32	1		T37	1		T60	3
auto[1]	auto[1]	valid[2]	auto[0]	80	1			T32	1		T35	1		T37	1
auto[1]	auto[1]	valid[3]	auto[0]	65	1			T32	1		T36	2		T52	1
auto[1]	auto[1]	valid[4]	auto[0]	71	1			T32	2		T35	1		T29	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal