Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	795	1			T37	12		T13	7		T16	14
all_values[1]	795	1			T37	12		T13	7		T16	14
all_values[2]	795	1			T37	12		T13	7		T16	14
all_values[3]	795	1			T37	12		T13	7		T16	14
all_values[4]	795	1			T37	12		T13	7		T16	14
all_values[5]	795	1			T37	12		T13	7		T16	14
all_values[6]	795	1			T37	12		T13	7		T16	14
all_values[7]	795	1			T37	12		T13	7		T16	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3413

1

T37

56

T13

33

T16

67

auto[1]

2947

1

T37

40

T13

23

T16

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2635

1

T37

42

T13

20

T16

46

auto[1]

3725

1

T37

54

T13

36

T16

66

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3713

1

T37

57

T13

33

T16

60

auto[1]

2647

1

T37

39

T13

23

T16

52

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	164	1			T37	2		T16	3		T18	3
all_values[0]	auto[0]	auto[0]	auto[1]	78	1			T37	2		T13	1		T16	1
all_values[0]	auto[0]	auto[1]	auto[0]	139	1			T37	2		T16	2		T17	2
all_values[0]	auto[0]	auto[1]	auto[1]	85	1			T37	2		T13	1		T17	3
all_values[0]	auto[1]	auto[0]	auto[1]	172	1			T37	1		T13	2		T16	5
all_values[0]	auto[1]	auto[1]	auto[1]	157	1			T37	3		T13	3		T16	3
all_values[1]	auto[0]	auto[0]	auto[0]	182	1			T37	3		T13	1		T16	2
all_values[1]	auto[0]	auto[0]	auto[1]	64	1			T37	2		T13	2		T16	1
all_values[1]	auto[0]	auto[1]	auto[0]	139	1			T37	2		T13	2		T17	2
all_values[1]	auto[0]	auto[1]	auto[1]	77	1			T16	1		T17	1		T18	1
all_values[1]	auto[1]	auto[0]	auto[1]	181	1			T37	4		T16	6		T17	4
all_values[1]	auto[1]	auto[1]	auto[1]	152	1			T37	1		T13	2		T16	4
all_values[2]	auto[0]	auto[0]	auto[0]	183	1			T37	4		T13	1		T16	2
all_values[2]	auto[0]	auto[0]	auto[1]	65	1			T37	1		T17	1		T18	1
all_values[2]	auto[0]	auto[1]	auto[0]	137	1			T37	1		T13	2		T16	3
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T13	2		T16	1		T17	1
all_values[2]	auto[1]	auto[0]	auto[1]	158	1			T37	2		T16	6		T17	3
all_values[2]	auto[1]	auto[1]	auto[1]	161	1			T37	4		T13	2		T16	2
all_values[3]	auto[0]	auto[0]	auto[0]	153	1			T13	1		T16	1		T17	1
all_values[3]	auto[0]	auto[0]	auto[1]	86	1			T13	1		T16	2		T18	2
all_values[3]	auto[0]	auto[1]	auto[0]	139	1			T37	1		T13	2		T16	2
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T37	4		T13	1		T16	2
all_values[3]	auto[1]	auto[0]	auto[1]	192	1			T37	3		T13	1		T16	3
all_values[3]	auto[1]	auto[1]	auto[1]	140	1			T37	4		T13	1		T16	4
all_values[4]	auto[0]	auto[0]	auto[0]	166	1			T37	3		T13	4		T16	4
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T37	2		T13	1		T16	1
all_values[4]	auto[0]	auto[1]	auto[0]	123	1			T16	4		T17	2		T18	4
all_values[4]	auto[0]	auto[1]	auto[1]	89	1			T37	1		T16	1		T17	1
all_values[4]	auto[1]	auto[0]	auto[1]	180	1			T37	4		T13	1		T16	2
all_values[4]	auto[1]	auto[1]	auto[1]	157	1			T37	2		T13	1		T16	2
all_values[5]	auto[0]	auto[0]	auto[0]	263	1			T37	6		T13	1		T16	6
all_values[5]	auto[0]	auto[1]	auto[0]	198	1			T37	1		T13	2		T16	4
all_values[5]	auto[1]	auto[0]	auto[1]	199	1			T37	4		T13	3		T16	2
all_values[5]	auto[1]	auto[1]	auto[1]	135	1			T37	1		T13	1		T16	2
all_values[6]	auto[0]	auto[0]	auto[0]	174	1			T37	6		T13	1		T16	7
all_values[6]	auto[0]	auto[0]	auto[1]	62	1			T13	1		T19	1		T20	2
all_values[6]	auto[0]	auto[1]	auto[0]	155	1			T37	4		T16	3		T17	3
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T13	1		T17	1		T18	4
all_values[6]	auto[1]	auto[0]	auto[1]	167	1			T37	2		T13	4		T16	3
all_values[6]	auto[1]	auto[1]	auto[1]	167	1			T16	1		T17	2		T18	5
all_values[7]	auto[0]	auto[0]	auto[0]	173	1			T37	2		T13	3		T16	2
all_values[7]	auto[0]	auto[0]	auto[1]	91	1			T13	2		T16	3		T17	3
all_values[7]	auto[0]	auto[1]	auto[0]	147	1			T37	5		T16	1		T17	1
all_values[7]	auto[0]	auto[1]	auto[1]	55	1			T37	1		T16	1		T17	1
all_values[7]	auto[1]	auto[0]	auto[1]	180	1			T37	3		T13	2		T16	5
all_values[7]	auto[1]	auto[1]	auto[1]	149	1			T37	1		T16	2		T17	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal