Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49499

1

T32

476

T35

360

T36

237

auto[1]

16352

1

T31

39

T33

364

T34

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47698

1

T31

39

T32

323

T33

364

auto[1]

18153

1

T32

153

T35

153

T36

99

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33730	1			T31	19		T32	250		T33	180
others[1]	5487	1			T31	2		T32	37		T33	37
others[2]	5613	1			T31	4		T32	40		T33	26
others[3]	6387	1			T31	5		T32	35		T33	39
interest[1]	3703	1			T31	3		T32	27		T33	24
interest[4]	22111	1			T31	10		T32	158		T33	107
interest[64]	10931	1			T31	6		T32	87		T33	58

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15921	1			T32	176		T35	98		T36	71
auto[0]	auto[0]	others[1]	2681	1			T32	23		T35	15		T36	17
auto[0]	auto[0]	others[2]	2655	1			T32	25		T35	21		T36	11
auto[0]	auto[0]	others[3]	3031	1			T32	21		T35	21		T36	12
auto[0]	auto[0]	interest[1]	1808	1			T32	18		T35	16		T36	5
auto[0]	auto[0]	interest[4]	10373	1			T32	114		T35	64		T36	44
auto[0]	auto[0]	interest[64]	5250	1			T32	60		T35	36		T36	22
auto[0]	auto[1]	others[0]	8514	1			T31	19		T33	180		T34	5
auto[0]	auto[1]	others[1]	1367	1			T31	2		T33	37		T35	7
auto[0]	auto[1]	others[2]	1382	1			T31	4		T33	26		T35	8
auto[0]	auto[1]	others[3]	1591	1			T31	5		T33	39		T35	7
auto[0]	auto[1]	interest[1]	878	1			T31	3		T33	24		T35	8
auto[0]	auto[1]	interest[4]	5660	1			T31	10		T33	107		T34	5
auto[0]	auto[1]	interest[64]	2620	1			T31	6		T33	58		T35	17
auto[1]	auto[0]	others[0]	9295	1			T32	74		T35	82		T36	55
auto[1]	auto[0]	others[1]	1439	1			T32	14		T35	7		T36	5
auto[1]	auto[0]	others[2]	1576	1			T32	15		T35	13		T36	11
auto[1]	auto[0]	others[3]	1765	1			T32	14		T35	19		T36	10
auto[1]	auto[0]	interest[1]	1017	1			T32	9		T35	6		T36	7
auto[1]	auto[0]	interest[4]	6078	1			T32	44		T35	60		T36	33
auto[1]	auto[0]	interest[64]	3061	1			T32	27		T35	26		T36	11

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal