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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.98 98.62 89.36 97.21 95.45 99.25


Total test records in report: 1081
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T1016 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2877985298 Jun 22 04:50:54 PM PDT 24 Jun 22 04:50:56 PM PDT 24 22061542 ps
T1017 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3976221196 Jun 22 04:50:40 PM PDT 24 Jun 22 04:50:41 PM PDT 24 23709605 ps
T1018 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.689539742 Jun 22 04:50:47 PM PDT 24 Jun 22 04:51:05 PM PDT 24 3241413020 ps
T1019 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2375607066 Jun 22 04:50:46 PM PDT 24 Jun 22 04:50:51 PM PDT 24 47939565 ps
T1020 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1799798501 Jun 22 04:50:36 PM PDT 24 Jun 22 04:50:38 PM PDT 24 14576255 ps
T108 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2364692401 Jun 22 04:50:52 PM PDT 24 Jun 22 04:50:55 PM PDT 24 94167566 ps
T113 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3799494347 Jun 22 04:50:52 PM PDT 24 Jun 22 04:50:56 PM PDT 24 95129133 ps
T117 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3434488781 Jun 22 04:50:51 PM PDT 24 Jun 22 04:50:55 PM PDT 24 54111704 ps
T1021 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.439328112 Jun 22 04:50:52 PM PDT 24 Jun 22 04:50:56 PM PDT 24 1656142805 ps
T184 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1816664892 Jun 22 04:50:31 PM PDT 24 Jun 22 04:50:44 PM PDT 24 196503617 ps
T1022 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1466489572 Jun 22 04:50:32 PM PDT 24 Jun 22 04:50:35 PM PDT 24 161812374 ps
T1023 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3370840475 Jun 22 04:50:47 PM PDT 24 Jun 22 04:50:52 PM PDT 24 157930652 ps
T1024 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.121741353 Jun 22 04:50:33 PM PDT 24 Jun 22 04:50:36 PM PDT 24 89952531 ps
T1025 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.601447996 Jun 22 04:51:02 PM PDT 24 Jun 22 04:51:03 PM PDT 24 44342466 ps
T1026 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3878489419 Jun 22 04:51:01 PM PDT 24 Jun 22 04:51:03 PM PDT 24 45819936 ps
T1027 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2913609938 Jun 22 04:50:48 PM PDT 24 Jun 22 04:50:50 PM PDT 24 11332047 ps
T120 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1722213794 Jun 22 04:50:35 PM PDT 24 Jun 22 04:50:39 PM PDT 24 90910950 ps
T1028 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3115078697 Jun 22 04:50:39 PM PDT 24 Jun 22 04:50:41 PM PDT 24 17875148 ps
T1029 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.439561807 Jun 22 04:51:01 PM PDT 24 Jun 22 04:51:02 PM PDT 24 11488511 ps
T1030 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3277627560 Jun 22 04:50:59 PM PDT 24 Jun 22 04:51:00 PM PDT 24 56931523 ps
T1031 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3093234271 Jun 22 04:50:34 PM PDT 24 Jun 22 04:50:36 PM PDT 24 52399338 ps
T109 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2512676150 Jun 22 04:50:40 PM PDT 24 Jun 22 04:50:43 PM PDT 24 126532521 ps
T181 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1285047133 Jun 22 04:50:58 PM PDT 24 Jun 22 04:51:21 PM PDT 24 822620078 ps
T1032 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4194803467 Jun 22 04:50:31 PM PDT 24 Jun 22 04:50:36 PM PDT 24 1242897835 ps
T1033 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1780551807 Jun 22 04:50:42 PM PDT 24 Jun 22 04:50:46 PM PDT 24 268318827 ps
T1034 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1036966630 Jun 22 04:50:44 PM PDT 24 Jun 22 04:50:48 PM PDT 24 226200205 ps
T1035 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1627216052 Jun 22 04:50:48 PM PDT 24 Jun 22 04:51:01 PM PDT 24 363659825 ps
T1036 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.582129042 Jun 22 04:50:55 PM PDT 24 Jun 22 04:50:56 PM PDT 24 17596148 ps
T182 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2016075843 Jun 22 04:50:48 PM PDT 24 Jun 22 04:50:56 PM PDT 24 427298390 ps
T1037 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3904141103 Jun 22 04:50:58 PM PDT 24 Jun 22 04:51:02 PM PDT 24 110677521 ps
T90 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2137915788 Jun 22 04:50:34 PM PDT 24 Jun 22 04:50:36 PM PDT 24 79386349 ps
T1038 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4150763749 Jun 22 04:50:32 PM PDT 24 Jun 22 04:50:41 PM PDT 24 205932972 ps
T1039 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.865423555 Jun 22 04:50:54 PM PDT 24 Jun 22 04:50:58 PM PDT 24 633897054 ps
T110 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2528963775 Jun 22 04:50:58 PM PDT 24 Jun 22 04:51:04 PM PDT 24 1272704647 ps
T1040 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3550598161 Jun 22 04:50:52 PM PDT 24 Jun 22 04:50:56 PM PDT 24 156604842 ps
T1041 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3968387048 Jun 22 04:50:38 PM PDT 24 Jun 22 04:50:41 PM PDT 24 297974137 ps
T1042 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.52797592 Jun 22 04:50:37 PM PDT 24 Jun 22 04:50:38 PM PDT 24 70558154 ps
T1043 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2960854252 Jun 22 04:50:45 PM PDT 24 Jun 22 04:50:47 PM PDT 24 11040907 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4219183916 Jun 22 04:50:43 PM PDT 24 Jun 22 04:50:45 PM PDT 24 116788991 ps
T114 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3078001373 Jun 22 04:50:53 PM PDT 24 Jun 22 04:50:56 PM PDT 24 1170105834 ps
T188 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1722495747 Jun 22 04:50:48 PM PDT 24 Jun 22 04:51:11 PM PDT 24 831987135 ps
T1045 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.699273947 Jun 22 04:50:37 PM PDT 24 Jun 22 04:50:56 PM PDT 24 1218541187 ps
T118 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3576293910 Jun 22 04:50:40 PM PDT 24 Jun 22 04:50:43 PM PDT 24 94026402 ps
T1046 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1696048821 Jun 22 04:50:50 PM PDT 24 Jun 22 04:51:13 PM PDT 24 4361113008 ps
T1047 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1300014018 Jun 22 04:50:55 PM PDT 24 Jun 22 04:50:58 PM PDT 24 495519114 ps
T1048 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2164166021 Jun 22 04:50:58 PM PDT 24 Jun 22 04:50:59 PM PDT 24 15397352 ps
T1049 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3360503627 Jun 22 04:50:32 PM PDT 24 Jun 22 04:50:36 PM PDT 24 202685985 ps
T1050 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2626353768 Jun 22 04:50:46 PM PDT 24 Jun 22 04:50:51 PM PDT 24 60980962 ps
T1051 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2443670501 Jun 22 04:50:40 PM PDT 24 Jun 22 04:50:42 PM PDT 24 107803012 ps
T1052 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2624723526 Jun 22 04:50:53 PM PDT 24 Jun 22 04:50:54 PM PDT 24 19771389 ps
T1053 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2734132300 Jun 22 04:50:36 PM PDT 24 Jun 22 04:50:38 PM PDT 24 19134566 ps
T1054 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2829665200 Jun 22 04:50:33 PM PDT 24 Jun 22 04:50:35 PM PDT 24 17050663 ps
T1055 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.625919547 Jun 22 04:51:01 PM PDT 24 Jun 22 04:51:03 PM PDT 24 14471854 ps
T1056 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3849262059 Jun 22 04:50:59 PM PDT 24 Jun 22 04:51:01 PM PDT 24 90323406 ps
T179 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3306515087 Jun 22 04:50:49 PM PDT 24 Jun 22 04:50:54 PM PDT 24 133050432 ps
T1057 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3944441932 Jun 22 04:50:52 PM PDT 24 Jun 22 04:50:54 PM PDT 24 132253758 ps
T119 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1356020343 Jun 22 04:50:32 PM PDT 24 Jun 22 04:50:37 PM PDT 24 185784687 ps
T1058 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3745319053 Jun 22 04:50:45 PM PDT 24 Jun 22 04:50:47 PM PDT 24 23639552 ps
T1059 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2667124617 Jun 22 04:50:34 PM PDT 24 Jun 22 04:50:37 PM PDT 24 82632304 ps
T1060 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4294472180 Jun 22 04:50:45 PM PDT 24 Jun 22 04:50:46 PM PDT 24 13895842 ps
T1061 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1463173888 Jun 22 04:50:33 PM PDT 24 Jun 22 04:50:36 PM PDT 24 60517792 ps
T1062 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.617744990 Jun 22 04:50:38 PM PDT 24 Jun 22 04:50:54 PM PDT 24 209317995 ps
T1063 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1385973446 Jun 22 04:51:00 PM PDT 24 Jun 22 04:51:01 PM PDT 24 15425006 ps
T1064 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.812327154 Jun 22 04:50:55 PM PDT 24 Jun 22 04:50:56 PM PDT 24 15375814 ps
T1065 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2513664009 Jun 22 04:50:33 PM PDT 24 Jun 22 04:50:38 PM PDT 24 225038475 ps
T1066 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1548576978 Jun 22 04:50:48 PM PDT 24 Jun 22 04:50:51 PM PDT 24 128836974 ps
T1067 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.710448613 Jun 22 04:51:03 PM PDT 24 Jun 22 04:51:05 PM PDT 24 40422917 ps
T1068 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3195990572 Jun 22 04:50:54 PM PDT 24 Jun 22 04:51:08 PM PDT 24 557057473 ps
T1069 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.30540940 Jun 22 04:50:34 PM PDT 24 Jun 22 04:50:37 PM PDT 24 55869277 ps
T1070 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.902969924 Jun 22 04:50:37 PM PDT 24 Jun 22 04:50:39 PM PDT 24 35516327 ps
T1071 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1177383054 Jun 22 04:50:42 PM PDT 24 Jun 22 04:50:44 PM PDT 24 20038931 ps
T1072 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4278678444 Jun 22 04:50:33 PM PDT 24 Jun 22 04:50:36 PM PDT 24 48226272 ps
T1073 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3309076716 Jun 22 04:50:40 PM PDT 24 Jun 22 04:50:56 PM PDT 24 5520715661 ps
T1074 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3143204401 Jun 22 04:50:59 PM PDT 24 Jun 22 04:51:00 PM PDT 24 18106550 ps
T1075 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4145940196 Jun 22 04:50:39 PM PDT 24 Jun 22 04:50:41 PM PDT 24 47814816 ps
T1076 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1648683377 Jun 22 04:50:54 PM PDT 24 Jun 22 04:50:55 PM PDT 24 51036811 ps
T1077 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.998480676 Jun 22 04:50:42 PM PDT 24 Jun 22 04:50:50 PM PDT 24 649530449 ps
T1078 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3065699426 Jun 22 04:50:45 PM PDT 24 Jun 22 04:50:47 PM PDT 24 157075104 ps
T1079 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.459729136 Jun 22 04:50:43 PM PDT 24 Jun 22 04:50:49 PM PDT 24 202317220 ps
T1080 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2921321716 Jun 22 04:50:41 PM PDT 24 Jun 22 04:50:45 PM PDT 24 41906578 ps
T1081 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1679046705 Jun 22 04:50:48 PM PDT 24 Jun 22 04:50:53 PM PDT 24 408275068 ps

Test location /workspace/coverage/default/19.spi_device_flash_all.793986874
Short name T1
Test name
Test status
Simulation time 5808606550 ps
CPU time 47.3 seconds
Started Jun 22 06:10:32 PM PDT 24
Finished Jun 22 06:11:20 PM PDT 24
Peak memory 253848 kb
Host smart-f359729b-e758-41bc-b210-5cd9601a3491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793986874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.793986874
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.163854714
Short name T35
Test name
Test status
Simulation time 9280242043 ps
CPU time 96.57 seconds
Started Jun 22 06:10:50 PM PDT 24
Finished Jun 22 06:12:28 PM PDT 24
Peak memory 257640 kb
Host smart-eff5ebb1-6629-494e-bd6f-bade3c00a9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163854714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.163854714
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2706079615
Short name T39
Test name
Test status
Simulation time 1736072637 ps
CPU time 34.55 seconds
Started Jun 22 06:10:23 PM PDT 24
Finished Jun 22 06:10:58 PM PDT 24
Peak memory 253456 kb
Host smart-5c5debe7-daa4-400e-b603-92cd8ab59d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706079615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2706079615
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2932348188
Short name T17
Test name
Test status
Simulation time 181501246076 ps
CPU time 462.28 seconds
Started Jun 22 06:11:04 PM PDT 24
Finished Jun 22 06:18:47 PM PDT 24
Peak memory 263848 kb
Host smart-01967ed1-4748-42b7-88d5-ad5e7fad7533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932348188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2932348188
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4131461632
Short name T99
Test name
Test status
Simulation time 1043478591 ps
CPU time 23.61 seconds
Started Jun 22 04:50:45 PM PDT 24
Finished Jun 22 04:51:10 PM PDT 24
Peak memory 216012 kb
Host smart-0fb88da0-6cde-46ff-b9d0-7d07a0110a35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131461632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.4131461632
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.4020941520
Short name T45
Test name
Test status
Simulation time 33174398520 ps
CPU time 376.09 seconds
Started Jun 22 06:11:42 PM PDT 24
Finished Jun 22 06:17:59 PM PDT 24
Peak memory 257564 kb
Host smart-3337de56-d294-4695-b003-d97f0f518fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020941520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.4020941520
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3237560389
Short name T13
Test name
Test status
Simulation time 97367890313 ps
CPU time 854.46 seconds
Started Jun 22 06:11:57 PM PDT 24
Finished Jun 22 06:26:12 PM PDT 24
Peak memory 289452 kb
Host smart-44c15db7-9331-4357-8f02-921fb49a1bdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237560389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3237560389
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2064204217
Short name T78
Test name
Test status
Simulation time 15560803 ps
CPU time 0.75 seconds
Started Jun 22 06:09:19 PM PDT 24
Finished Jun 22 06:09:20 PM PDT 24
Peak memory 216224 kb
Host smart-4c682a21-cfc5-4aae-bb63-68bb1b349301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064204217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2064204217
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1551894840
Short name T55
Test name
Test status
Simulation time 29009208880 ps
CPU time 241.49 seconds
Started Jun 22 06:11:10 PM PDT 24
Finished Jun 22 06:15:12 PM PDT 24
Peak memory 257624 kb
Host smart-b57727a9-19cc-4434-bcc9-cedddb497c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551894840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1551894840
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2238870203
Short name T21
Test name
Test status
Simulation time 7737367463 ps
CPU time 130.08 seconds
Started Jun 22 06:09:21 PM PDT 24
Finished Jun 22 06:11:32 PM PDT 24
Peak memory 273812 kb
Host smart-865296c2-7863-4fc1-90f5-dadb0cedf36f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238870203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2238870203
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3648007792
Short name T27
Test name
Test status
Simulation time 65283454462 ps
CPU time 168.7 seconds
Started Jun 22 06:11:39 PM PDT 24
Finished Jun 22 06:14:29 PM PDT 24
Peak memory 257368 kb
Host smart-92bfa7a3-1914-448c-8fce-b383440939f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648007792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3648007792
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1458720318
Short name T100
Test name
Test status
Simulation time 138650349 ps
CPU time 3.63 seconds
Started Jun 22 04:50:42 PM PDT 24
Finished Jun 22 04:50:47 PM PDT 24
Peak memory 216136 kb
Host smart-50abbeb3-a1a0-4712-98b1-dcebb6c9ca4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458720318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
458720318
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.918670198
Short name T52
Test name
Test status
Simulation time 440422526019 ps
CPU time 373.69 seconds
Started Jun 22 06:10:29 PM PDT 24
Finished Jun 22 06:16:43 PM PDT 24
Peak memory 256848 kb
Host smart-973e69b3-08ab-4ba6-8869-7498c0a8418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918670198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.918670198
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.965214846
Short name T12
Test name
Test status
Simulation time 1402721889 ps
CPU time 1.27 seconds
Started Jun 22 06:09:28 PM PDT 24
Finished Jun 22 06:09:30 PM PDT 24
Peak memory 235516 kb
Host smart-8c223ca6-37e7-45e6-93f1-9ea39d99a50d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965214846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.965214846
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3013753053
Short name T61
Test name
Test status
Simulation time 141382247031 ps
CPU time 1470.29 seconds
Started Jun 22 06:10:59 PM PDT 24
Finished Jun 22 06:35:30 PM PDT 24
Peak memory 284200 kb
Host smart-11d1a889-c2a8-4905-a129-b66f486b007d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013753053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3013753053
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1315712968
Short name T7
Test name
Test status
Simulation time 106993355 ps
CPU time 5.24 seconds
Started Jun 22 06:09:28 PM PDT 24
Finished Jun 22 06:09:34 PM PDT 24
Peak memory 224572 kb
Host smart-6d5c76a6-b0bf-4dce-95b3-b50bb44a0c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315712968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1315712968
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.921991654
Short name T201
Test name
Test status
Simulation time 128789299111 ps
CPU time 452.39 seconds
Started Jun 22 06:12:02 PM PDT 24
Finished Jun 22 06:19:35 PM PDT 24
Peak memory 255672 kb
Host smart-d03c25f4-965f-4cf6-80aa-a8b7a4591272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921991654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.921991654
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2493081980
Short name T243
Test name
Test status
Simulation time 15905983622 ps
CPU time 208.85 seconds
Started Jun 22 06:11:22 PM PDT 24
Finished Jun 22 06:14:52 PM PDT 24
Peak memory 253488 kb
Host smart-048f3c7c-cdec-4585-8fa4-4633f04bb4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493081980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2493081980
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3801090188
Short name T88
Test name
Test status
Simulation time 25404712 ps
CPU time 1.02 seconds
Started Jun 22 04:50:33 PM PDT 24
Finished Jun 22 04:50:35 PM PDT 24
Peak memory 207556 kb
Host smart-226e6e0a-4c34-4b0f-bb42-bd44441da8d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801090188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3801090188
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2703347568
Short name T84
Test name
Test status
Simulation time 33915465922 ps
CPU time 111.47 seconds
Started Jun 22 06:09:36 PM PDT 24
Finished Jun 22 06:11:29 PM PDT 24
Peak memory 249436 kb
Host smart-082fdb9e-83b3-4450-8226-728631c746ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703347568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2703347568
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1045803251
Short name T173
Test name
Test status
Simulation time 115579676311 ps
CPU time 395.17 seconds
Started Jun 22 06:11:14 PM PDT 24
Finished Jun 22 06:17:50 PM PDT 24
Peak memory 263788 kb
Host smart-7df4a491-2a55-4cc0-9c61-a7b943b27586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045803251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1045803251
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3870691646
Short name T18
Test name
Test status
Simulation time 5770071512 ps
CPU time 104.53 seconds
Started Jun 22 06:09:50 PM PDT 24
Finished Jun 22 06:11:35 PM PDT 24
Peak memory 257128 kb
Host smart-9f6b6209-de70-4a5d-a71b-cdeb0d66770a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870691646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3870691646
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.4144472798
Short name T148
Test name
Test status
Simulation time 382458855122 ps
CPU time 965.42 seconds
Started Jun 22 06:11:44 PM PDT 24
Finished Jun 22 06:27:50 PM PDT 24
Peak memory 282224 kb
Host smart-9e0201a1-51e5-4570-9126-c55a9e3ae157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144472798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.4144472798
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.4115487411
Short name T198
Test name
Test status
Simulation time 4198800866 ps
CPU time 95.61 seconds
Started Jun 22 06:10:02 PM PDT 24
Finished Jun 22 06:11:38 PM PDT 24
Peak memory 257532 kb
Host smart-17f458dc-41f3-4ea4-89b0-cf3a72d1587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115487411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4115487411
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2993377935
Short name T254
Test name
Test status
Simulation time 7303183233 ps
CPU time 128.17 seconds
Started Jun 22 06:12:25 PM PDT 24
Finished Jun 22 06:14:33 PM PDT 24
Peak memory 264540 kb
Host smart-225ba689-3b28-4b24-9d9a-fdf00ebe1dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993377935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2993377935
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.173679250
Short name T203
Test name
Test status
Simulation time 20176496647 ps
CPU time 157.75 seconds
Started Jun 22 06:12:28 PM PDT 24
Finished Jun 22 06:15:07 PM PDT 24
Peak memory 265816 kb
Host smart-db989b2a-fe79-4c12-8f62-67275c02c9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173679250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.173679250
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1587082486
Short name T143
Test name
Test status
Simulation time 13516222 ps
CPU time 0.77 seconds
Started Jun 22 06:10:09 PM PDT 24
Finished Jun 22 06:10:11 PM PDT 24
Peak memory 205532 kb
Host smart-983595e5-6e10-4943-9f80-356683e19cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587082486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1587082486
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2295595563
Short name T318
Test name
Test status
Simulation time 891245724 ps
CPU time 12.98 seconds
Started Jun 22 06:11:33 PM PDT 24
Finished Jun 22 06:11:46 PM PDT 24
Peak memory 232884 kb
Host smart-6cfb1b63-4a45-4df5-bc12-d527c37f2896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295595563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2295595563
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4195077097
Short name T194
Test name
Test status
Simulation time 71959357228 ps
CPU time 311.66 seconds
Started Jun 22 06:09:27 PM PDT 24
Finished Jun 22 06:14:39 PM PDT 24
Peak memory 265380 kb
Host smart-b42f554f-12ec-4b20-9bfc-b599f34e26ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195077097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4195077097
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3146949666
Short name T245
Test name
Test status
Simulation time 18548040827 ps
CPU time 262.75 seconds
Started Jun 22 06:10:09 PM PDT 24
Finished Jun 22 06:14:33 PM PDT 24
Peak memory 269556 kb
Host smart-8493e508-8f64-42fe-979b-90bb0905a8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146949666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3146949666
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1285047133
Short name T181
Test name
Test status
Simulation time 822620078 ps
CPU time 22.17 seconds
Started Jun 22 04:50:58 PM PDT 24
Finished Jun 22 04:51:21 PM PDT 24
Peak memory 216488 kb
Host smart-9ba2f386-b1f3-4e85-aa12-1f19441fe817
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285047133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1285047133
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.358981867
Short name T210
Test name
Test status
Simulation time 3725457676 ps
CPU time 86.44 seconds
Started Jun 22 06:10:50 PM PDT 24
Finished Jun 22 06:12:18 PM PDT 24
Peak memory 273940 kb
Host smart-677fcd1e-b0ef-48c5-bad9-a90ea329595a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358981867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.358981867
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.483563472
Short name T288
Test name
Test status
Simulation time 92774283486 ps
CPU time 288.28 seconds
Started Jun 22 06:10:53 PM PDT 24
Finished Jun 22 06:15:42 PM PDT 24
Peak memory 257312 kb
Host smart-ccb82278-4612-4a5c-b3fe-914daa7d4d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483563472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.483563472
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3306515087
Short name T179
Test name
Test status
Simulation time 133050432 ps
CPU time 4.2 seconds
Started Jun 22 04:50:49 PM PDT 24
Finished Jun 22 04:50:54 PM PDT 24
Peak memory 216208 kb
Host smart-82400d0e-8be8-412b-ad8a-c215c6b75a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306515087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3306515087
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3195990572
Short name T1068
Test name
Test status
Simulation time 557057473 ps
CPU time 13.82 seconds
Started Jun 22 04:50:54 PM PDT 24
Finished Jun 22 04:51:08 PM PDT 24
Peak memory 216004 kb
Host smart-39aabd59-64ba-4f8d-8b61-6b6a827dc6c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195990572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3195990572
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2046937792
Short name T38
Test name
Test status
Simulation time 64584073200 ps
CPU time 151.66 seconds
Started Jun 22 06:10:23 PM PDT 24
Finished Jun 22 06:12:55 PM PDT 24
Peak memory 250776 kb
Host smart-f41051e9-40fe-4e30-9e65-fefc89fc4a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046937792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2046937792
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1306418032
Short name T286
Test name
Test status
Simulation time 10652286301 ps
CPU time 141.7 seconds
Started Jun 22 06:10:30 PM PDT 24
Finished Jun 22 06:12:53 PM PDT 24
Peak memory 260252 kb
Host smart-fa65d44f-59f3-434a-a303-8aeb5bab16a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306418032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1306418032
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1233136594
Short name T44
Test name
Test status
Simulation time 155935861497 ps
CPU time 237.83 seconds
Started Jun 22 06:11:09 PM PDT 24
Finished Jun 22 06:15:08 PM PDT 24
Peak memory 265008 kb
Host smart-7b2f66d8-810a-422b-a25e-61668f83f958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233136594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1233136594
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.4040993035
Short name T96
Test name
Test status
Simulation time 839076174 ps
CPU time 5.14 seconds
Started Jun 22 06:10:12 PM PDT 24
Finished Jun 22 06:10:18 PM PDT 24
Peak memory 222928 kb
Host smart-27cfe1f3-e098-4321-bbca-6d991e485c3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4040993035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.4040993035
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.700298644
Short name T156
Test name
Test status
Simulation time 233146785 ps
CPU time 4.78 seconds
Started Jun 22 06:10:03 PM PDT 24
Finished Jun 22 06:10:08 PM PDT 24
Peak memory 219176 kb
Host smart-4ade24e3-4a31-4728-9f97-47ec195fb8b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=700298644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.700298644
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1816664892
Short name T184
Test name
Test status
Simulation time 196503617 ps
CPU time 11.89 seconds
Started Jun 22 04:50:31 PM PDT 24
Finished Jun 22 04:50:44 PM PDT 24
Peak memory 216156 kb
Host smart-c736358a-abf4-4ca8-ac04-7800f7fb6292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816664892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1816664892
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2624192751
Short name T312
Test name
Test status
Simulation time 70353520226 ps
CPU time 63.36 seconds
Started Jun 22 06:10:01 PM PDT 24
Finished Jun 22 06:11:05 PM PDT 24
Peak memory 249304 kb
Host smart-e9d8adf0-94c2-4916-80e7-b7e456df6ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624192751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2624192751
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2184514311
Short name T230
Test name
Test status
Simulation time 48484957730 ps
CPU time 160.71 seconds
Started Jun 22 06:10:12 PM PDT 24
Finished Jun 22 06:12:53 PM PDT 24
Peak memory 265992 kb
Host smart-6f5cea0b-6788-460a-8d55-ec2e33c13f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184514311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2184514311
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2108001234
Short name T216
Test name
Test status
Simulation time 90346537838 ps
CPU time 114.97 seconds
Started Jun 22 06:10:45 PM PDT 24
Finished Jun 22 06:12:41 PM PDT 24
Peak memory 257624 kb
Host smart-05a6fd4e-be25-4e52-bb02-10bba142bfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108001234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2108001234
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1356020343
Short name T119
Test name
Test status
Simulation time 185784687 ps
CPU time 4.79 seconds
Started Jun 22 04:50:32 PM PDT 24
Finished Jun 22 04:50:37 PM PDT 24
Peak memory 216132 kb
Host smart-a6ba3296-693d-449e-bee5-944a07694d33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356020343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
356020343
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.747422233
Short name T11
Test name
Test status
Simulation time 258427746 ps
CPU time 5.83 seconds
Started Jun 22 06:10:10 PM PDT 24
Finished Jun 22 06:10:16 PM PDT 24
Peak memory 241056 kb
Host smart-cc3dfd57-ba55-4246-9a8a-6cbbaa44243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747422233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.747422233
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4246805543
Short name T97
Test name
Test status
Simulation time 3427073316 ps
CPU time 66.61 seconds
Started Jun 22 06:10:49 PM PDT 24
Finished Jun 22 06:11:56 PM PDT 24
Peak memory 249452 kb
Host smart-e47f0872-bbfd-4698-86c8-afdabfbb0b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246805543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4246805543
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3576293910
Short name T118
Test name
Test status
Simulation time 94026402 ps
CPU time 2.86 seconds
Started Jun 22 04:50:40 PM PDT 24
Finished Jun 22 04:50:43 PM PDT 24
Peak memory 217124 kb
Host smart-79c592fc-da51-48aa-9930-42aa70a55777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576293910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3576293910
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.512307556
Short name T150
Test name
Test status
Simulation time 150382485682 ps
CPU time 353.83 seconds
Started Jun 22 06:09:34 PM PDT 24
Finished Jun 22 06:15:28 PM PDT 24
Peak memory 265628 kb
Host smart-82fe912d-925b-4676-851e-5f25c45732aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512307556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.512307556
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3536255822
Short name T130
Test name
Test status
Simulation time 318268787 ps
CPU time 7.87 seconds
Started Jun 22 04:50:31 PM PDT 24
Finished Jun 22 04:50:39 PM PDT 24
Peak memory 207704 kb
Host smart-c9db8ea4-8e83-4b5b-8333-fde61d3aa5c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536255822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3536255822
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.652422795
Short name T128
Test name
Test status
Simulation time 370328883 ps
CPU time 11.36 seconds
Started Jun 22 04:50:33 PM PDT 24
Finished Jun 22 04:50:46 PM PDT 24
Peak memory 207676 kb
Host smart-d2f08fcb-5e0c-4d26-9601-102e774569b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652422795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.652422795
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.197651203
Short name T966
Test name
Test status
Simulation time 23283825 ps
CPU time 0.94 seconds
Started Jun 22 04:50:35 PM PDT 24
Finished Jun 22 04:50:36 PM PDT 24
Peak memory 207488 kb
Host smart-8c39d419-e98a-4675-b1d0-80063231c924
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197651203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.197651203
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1087612555
Short name T75
Test name
Test status
Simulation time 102601218 ps
CPU time 3.59 seconds
Started Jun 22 04:50:36 PM PDT 24
Finished Jun 22 04:50:41 PM PDT 24
Peak memory 218868 kb
Host smart-5c5093b9-ae5e-46b1-9bd9-237fd170421c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087612555 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1087612555
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3468935295
Short name T1006
Test name
Test status
Simulation time 45558773 ps
CPU time 1.36 seconds
Started Jun 22 04:50:32 PM PDT 24
Finished Jun 22 04:50:34 PM PDT 24
Peak memory 215932 kb
Host smart-f1d8be6d-0119-4b68-ae13-feb296ffe284
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468935295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
468935295
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2829665200
Short name T1054
Test name
Test status
Simulation time 17050663 ps
CPU time 0.8 seconds
Started Jun 22 04:50:33 PM PDT 24
Finished Jun 22 04:50:35 PM PDT 24
Peak memory 204540 kb
Host smart-1e15af47-c9d3-45b4-8f5a-e85a45b58e71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829665200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
829665200
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.972646453
Short name T129
Test name
Test status
Simulation time 30425415 ps
CPU time 1.23 seconds
Started Jun 22 04:50:29 PM PDT 24
Finished Jun 22 04:50:31 PM PDT 24
Peak memory 215908 kb
Host smart-f3ff0e95-c63b-4175-89da-76371e290315
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972646453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.972646453
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.902969924
Short name T1070
Test name
Test status
Simulation time 35516327 ps
CPU time 0.65 seconds
Started Jun 22 04:50:37 PM PDT 24
Finished Jun 22 04:50:39 PM PDT 24
Peak memory 204296 kb
Host smart-186e7be9-9bcf-41fc-940b-2aa2af5689d7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902969924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.902969924
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4172907167
Short name T157
Test name
Test status
Simulation time 410488348 ps
CPU time 1.92 seconds
Started Jun 22 04:50:34 PM PDT 24
Finished Jun 22 04:50:37 PM PDT 24
Peak memory 215928 kb
Host smart-2acb3fc5-8d81-4781-b877-e392d906fcfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172907167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.4172907167
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.699273947
Short name T1045
Test name
Test status
Simulation time 1218541187 ps
CPU time 18.52 seconds
Started Jun 22 04:50:37 PM PDT 24
Finished Jun 22 04:50:56 PM PDT 24
Peak memory 215952 kb
Host smart-a24abf1a-e6ff-42cf-96b1-37615cd10927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699273947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.699273947
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4138040992
Short name T136
Test name
Test status
Simulation time 711121622 ps
CPU time 7.71 seconds
Started Jun 22 04:50:40 PM PDT 24
Finished Jun 22 04:50:49 PM PDT 24
Peak memory 215844 kb
Host smart-ddb7248f-da3f-404c-be75-7fc98b6ba00b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138040992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4138040992
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1627216052
Short name T1035
Test name
Test status
Simulation time 363659825 ps
CPU time 11.83 seconds
Started Jun 22 04:50:48 PM PDT 24
Finished Jun 22 04:51:01 PM PDT 24
Peak memory 207712 kb
Host smart-d7d34873-4b10-4231-bb34-76fcc6dbaaef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627216052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1627216052
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3360503627
Short name T1049
Test name
Test status
Simulation time 202685985 ps
CPU time 3.58 seconds
Started Jun 22 04:50:32 PM PDT 24
Finished Jun 22 04:50:36 PM PDT 24
Peak memory 218200 kb
Host smart-f1bffe92-92a8-4601-83d9-54d9f716eb27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360503627 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3360503627
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.121741353
Short name T1024
Test name
Test status
Simulation time 89952531 ps
CPU time 1.32 seconds
Started Jun 22 04:50:33 PM PDT 24
Finished Jun 22 04:50:36 PM PDT 24
Peak memory 207616 kb
Host smart-8acd756f-5685-4b8f-80c7-8ef1ad1bd635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121741353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.121741353
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.52797592
Short name T1042
Test name
Test status
Simulation time 70558154 ps
CPU time 0.69 seconds
Started Jun 22 04:50:37 PM PDT 24
Finished Jun 22 04:50:38 PM PDT 24
Peak memory 204368 kb
Host smart-eeeea6c5-f2a9-4d38-86d0-33cee5937314
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52797592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.52797592
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2734132300
Short name T1053
Test name
Test status
Simulation time 19134566 ps
CPU time 1.29 seconds
Started Jun 22 04:50:36 PM PDT 24
Finished Jun 22 04:50:38 PM PDT 24
Peak memory 215904 kb
Host smart-fe550007-5208-45d7-8e94-10bb74c892fc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734132300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2734132300
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3070668084
Short name T1014
Test name
Test status
Simulation time 11177216 ps
CPU time 0.72 seconds
Started Jun 22 04:50:37 PM PDT 24
Finished Jun 22 04:50:39 PM PDT 24
Peak memory 204512 kb
Host smart-6aab2e58-9bd6-4fa2-9f7a-9a4af4539b06
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070668084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3070668084
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1558380035
Short name T983
Test name
Test status
Simulation time 28239357 ps
CPU time 1.95 seconds
Started Jun 22 04:50:35 PM PDT 24
Finished Jun 22 04:50:38 PM PDT 24
Peak memory 215888 kb
Host smart-155e2fb6-cd17-4e59-a730-ccc35ce2e914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558380035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1558380035
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.30540940
Short name T1069
Test name
Test status
Simulation time 55869277 ps
CPU time 1.67 seconds
Started Jun 22 04:50:34 PM PDT 24
Finished Jun 22 04:50:37 PM PDT 24
Peak memory 215988 kb
Host smart-55ae451a-22ce-40e9-9ef2-abf4abfcd36f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30540940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.30540940
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.804884093
Short name T101
Test name
Test status
Simulation time 1337845865 ps
CPU time 7.57 seconds
Started Jun 22 04:50:34 PM PDT 24
Finished Jun 22 04:50:43 PM PDT 24
Peak memory 216384 kb
Host smart-b0b8af6e-9991-4a2b-a989-9b7b68340f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804884093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.804884093
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.607660782
Short name T122
Test name
Test status
Simulation time 78347309 ps
CPU time 2.45 seconds
Started Jun 22 04:50:40 PM PDT 24
Finished Jun 22 04:50:43 PM PDT 24
Peak memory 217096 kb
Host smart-d8a5cfd4-1d9e-4885-8d79-4d7f6ff3f975
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607660782 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.607660782
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3968387048
Short name T1041
Test name
Test status
Simulation time 297974137 ps
CPU time 1.87 seconds
Started Jun 22 04:50:38 PM PDT 24
Finished Jun 22 04:50:41 PM PDT 24
Peak memory 207636 kb
Host smart-d5530000-2846-415a-b201-38993181d15c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968387048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3968387048
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2443670501
Short name T1051
Test name
Test status
Simulation time 107803012 ps
CPU time 0.72 seconds
Started Jun 22 04:50:40 PM PDT 24
Finished Jun 22 04:50:42 PM PDT 24
Peak memory 204360 kb
Host smart-212031b0-f13b-45d8-b13e-2a94689d8fcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443670501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2443670501
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1036966630
Short name T1034
Test name
Test status
Simulation time 226200205 ps
CPU time 3.87 seconds
Started Jun 22 04:50:44 PM PDT 24
Finished Jun 22 04:50:48 PM PDT 24
Peak memory 215940 kb
Host smart-1b081519-45bc-40ce-a87f-a9c82f62d9d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036966630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1036966630
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3309076716
Short name T1073
Test name
Test status
Simulation time 5520715661 ps
CPU time 15.84 seconds
Started Jun 22 04:50:40 PM PDT 24
Finished Jun 22 04:50:56 PM PDT 24
Peak memory 215952 kb
Host smart-e5eb3600-5dda-465a-af82-9c5e77f27593
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309076716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3309076716
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2626353768
Short name T1050
Test name
Test status
Simulation time 60980962 ps
CPU time 3.83 seconds
Started Jun 22 04:50:46 PM PDT 24
Finished Jun 22 04:50:51 PM PDT 24
Peak memory 218736 kb
Host smart-2bb4ee0e-6375-4cb3-80ed-55dba8ef4f51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626353768 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2626353768
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3201502210
Short name T124
Test name
Test status
Simulation time 140597773 ps
CPU time 2.07 seconds
Started Jun 22 04:50:46 PM PDT 24
Finished Jun 22 04:50:49 PM PDT 24
Peak memory 207724 kb
Host smart-2d1564b4-0176-4c58-b472-27a8332c8dce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201502210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3201502210
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4294472180
Short name T1060
Test name
Test status
Simulation time 13895842 ps
CPU time 0.72 seconds
Started Jun 22 04:50:45 PM PDT 24
Finished Jun 22 04:50:46 PM PDT 24
Peak memory 204500 kb
Host smart-559573de-ea8f-438e-8ab6-3a19413ae487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294472180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4294472180
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3169923051
Short name T989
Test name
Test status
Simulation time 117592292 ps
CPU time 3.35 seconds
Started Jun 22 04:50:54 PM PDT 24
Finished Jun 22 04:50:58 PM PDT 24
Peak memory 215892 kb
Host smart-e79fb979-03cc-49c8-bafe-7f1276971674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169923051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3169923051
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1609409381
Short name T111
Test name
Test status
Simulation time 27608098 ps
CPU time 1.57 seconds
Started Jun 22 04:50:47 PM PDT 24
Finished Jun 22 04:50:50 PM PDT 24
Peak memory 216140 kb
Host smart-87177388-7dca-4fc9-b13e-01d453bccdab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609409381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1609409381
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2921969587
Short name T116
Test name
Test status
Simulation time 3770218491 ps
CPU time 21.91 seconds
Started Jun 22 04:50:45 PM PDT 24
Finished Jun 22 04:51:08 PM PDT 24
Peak memory 216168 kb
Host smart-a3ab295e-0e67-4ece-ab9e-892dd6d730a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921969587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2921969587
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2375607066
Short name T1019
Test name
Test status
Simulation time 47939565 ps
CPU time 3.22 seconds
Started Jun 22 04:50:46 PM PDT 24
Finished Jun 22 04:50:51 PM PDT 24
Peak memory 218740 kb
Host smart-47da913b-b866-4292-8450-d7c817b3de2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375607066 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2375607066
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2167803082
Short name T135
Test name
Test status
Simulation time 110330320 ps
CPU time 1.83 seconds
Started Jun 22 04:50:55 PM PDT 24
Finished Jun 22 04:50:57 PM PDT 24
Peak memory 207536 kb
Host smart-4fb3949b-be52-4866-9e81-d9927d2653e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167803082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2167803082
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2270683833
Short name T964
Test name
Test status
Simulation time 13159469 ps
CPU time 0.7 seconds
Started Jun 22 04:50:47 PM PDT 24
Finished Jun 22 04:50:48 PM PDT 24
Peak memory 204376 kb
Host smart-689c7b6c-fd24-49c3-b22c-a251744a6c1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270683833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2270683833
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3542836702
Short name T160
Test name
Test status
Simulation time 136992899 ps
CPU time 2.98 seconds
Started Jun 22 04:50:48 PM PDT 24
Finished Jun 22 04:50:52 PM PDT 24
Peak memory 215832 kb
Host smart-066686fd-ec0c-4bd2-9040-97971f4e1b6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542836702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3542836702
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1940132434
Short name T187
Test name
Test status
Simulation time 2352686570 ps
CPU time 14.06 seconds
Started Jun 22 04:50:45 PM PDT 24
Finished Jun 22 04:51:00 PM PDT 24
Peak memory 215992 kb
Host smart-6c439a56-105c-4542-a339-df48f5c3b37f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940132434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1940132434
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2856396961
Short name T76
Test name
Test status
Simulation time 40047006 ps
CPU time 2.68 seconds
Started Jun 22 04:52:59 PM PDT 24
Finished Jun 22 04:53:02 PM PDT 24
Peak memory 217028 kb
Host smart-bc6858c0-d785-442d-9968-a48e538c87c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856396961 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2856396961
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3944441932
Short name T1057
Test name
Test status
Simulation time 132253758 ps
CPU time 1.77 seconds
Started Jun 22 04:50:52 PM PDT 24
Finished Jun 22 04:50:54 PM PDT 24
Peak memory 207840 kb
Host smart-17c8a84a-0ce0-4f7e-b41c-7a04da357852
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944441932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3944441932
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.738376470
Short name T1001
Test name
Test status
Simulation time 22838180 ps
CPU time 0.77 seconds
Started Jun 22 04:50:45 PM PDT 24
Finished Jun 22 04:50:47 PM PDT 24
Peak memory 204352 kb
Host smart-c037bd17-c9a5-4806-831c-b0e02e3beeee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738376470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.738376470
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.439328112
Short name T1021
Test name
Test status
Simulation time 1656142805 ps
CPU time 2.97 seconds
Started Jun 22 04:50:52 PM PDT 24
Finished Jun 22 04:50:56 PM PDT 24
Peak memory 215976 kb
Host smart-d9457e65-d394-48d1-8b4d-481fd5b67336
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439328112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.439328112
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2649653683
Short name T98
Test name
Test status
Simulation time 50798191 ps
CPU time 3.19 seconds
Started Jun 22 04:51:54 PM PDT 24
Finished Jun 22 04:51:59 PM PDT 24
Peak memory 216200 kb
Host smart-0a6eb4bd-2c5d-427f-8bbf-51ab668a23dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649653683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2649653683
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.421962833
Short name T183
Test name
Test status
Simulation time 334078874 ps
CPU time 7.21 seconds
Started Jun 22 04:50:55 PM PDT 24
Finished Jun 22 04:51:03 PM PDT 24
Peak memory 215764 kb
Host smart-61dbfecc-5f42-40ae-971b-a4927d079e82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421962833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.421962833
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1127137128
Short name T77
Test name
Test status
Simulation time 458537530 ps
CPU time 3.25 seconds
Started Jun 22 04:50:45 PM PDT 24
Finished Jun 22 04:50:48 PM PDT 24
Peak memory 219236 kb
Host smart-92e0b91b-80ab-417a-9253-e3b118d2a5a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127137128 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1127137128
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2937889161
Short name T1003
Test name
Test status
Simulation time 221636836 ps
CPU time 2.72 seconds
Started Jun 22 04:50:55 PM PDT 24
Finished Jun 22 04:50:58 PM PDT 24
Peak memory 215832 kb
Host smart-8344d1ba-9129-44a9-8fd7-0cf17923f73b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937889161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2937889161
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2913609938
Short name T1027
Test name
Test status
Simulation time 11332047 ps
CPU time 0.75 seconds
Started Jun 22 04:50:48 PM PDT 24
Finished Jun 22 04:50:50 PM PDT 24
Peak memory 204688 kb
Host smart-b4ddf18a-fedf-4761-8854-b0b5ed6468ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913609938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2913609938
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.286317972
Short name T159
Test name
Test status
Simulation time 149192158 ps
CPU time 3.3 seconds
Started Jun 22 04:50:51 PM PDT 24
Finished Jun 22 04:50:55 PM PDT 24
Peak memory 216008 kb
Host smart-66b164de-50bf-4341-b02b-d7a7822ed94b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286317972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.286317972
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2364692401
Short name T108
Test name
Test status
Simulation time 94167566 ps
CPU time 2.99 seconds
Started Jun 22 04:50:52 PM PDT 24
Finished Jun 22 04:50:55 PM PDT 24
Peak memory 216144 kb
Host smart-12f28d92-2d37-4788-bd79-afb0f1e88262
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364692401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2364692401
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.431100901
Short name T1012
Test name
Test status
Simulation time 210522476 ps
CPU time 6.34 seconds
Started Jun 22 04:50:46 PM PDT 24
Finished Jun 22 04:50:54 PM PDT 24
Peak memory 215896 kb
Host smart-5a2f59f9-367f-4c50-89e8-8f0d01f47eda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431100901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.431100901
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3550598161
Short name T1040
Test name
Test status
Simulation time 156604842 ps
CPU time 3.39 seconds
Started Jun 22 04:50:52 PM PDT 24
Finished Jun 22 04:50:56 PM PDT 24
Peak memory 219688 kb
Host smart-0f2b6294-84b1-43f9-a12c-5f4f179d0077
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550598161 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3550598161
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3155555618
Short name T1002
Test name
Test status
Simulation time 440640018 ps
CPU time 1.27 seconds
Started Jun 22 04:50:47 PM PDT 24
Finished Jun 22 04:50:49 PM PDT 24
Peak memory 219736 kb
Host smart-091a4507-a440-449a-b50f-ed68ff5cca71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155555618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3155555618
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3745319053
Short name T1058
Test name
Test status
Simulation time 23639552 ps
CPU time 0.7 seconds
Started Jun 22 04:50:45 PM PDT 24
Finished Jun 22 04:50:47 PM PDT 24
Peak memory 204364 kb
Host smart-78650db2-d2c6-4620-8351-afec65c17d78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745319053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3745319053
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2757621113
Short name T1007
Test name
Test status
Simulation time 435887254 ps
CPU time 2.99 seconds
Started Jun 22 04:50:46 PM PDT 24
Finished Jun 22 04:50:50 PM PDT 24
Peak memory 215972 kb
Host smart-72936751-987b-4172-8cf9-14e398fd90c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757621113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2757621113
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3799494347
Short name T113
Test name
Test status
Simulation time 95129133 ps
CPU time 2.87 seconds
Started Jun 22 04:50:52 PM PDT 24
Finished Jun 22 04:50:56 PM PDT 24
Peak memory 215952 kb
Host smart-b2722074-c123-4b70-9ff2-cc22d3c4c951
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799494347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3799494347
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1696048821
Short name T1046
Test name
Test status
Simulation time 4361113008 ps
CPU time 22.39 seconds
Started Jun 22 04:50:50 PM PDT 24
Finished Jun 22 04:51:13 PM PDT 24
Peak memory 215976 kb
Host smart-d111ce97-579e-4a2f-80a9-6842cbc31b7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696048821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1696048821
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.739966187
Short name T1013
Test name
Test status
Simulation time 49587771 ps
CPU time 3.36 seconds
Started Jun 22 04:50:53 PM PDT 24
Finished Jun 22 04:50:57 PM PDT 24
Peak memory 218580 kb
Host smart-6c8a5a8e-b00c-4af4-b2e8-4dfdebb05dda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739966187 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.739966187
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.919643264
Short name T131
Test name
Test status
Simulation time 20927216 ps
CPU time 1.27 seconds
Started Jun 22 04:50:53 PM PDT 24
Finished Jun 22 04:50:54 PM PDT 24
Peak memory 207704 kb
Host smart-bb93158f-e153-4bab-905a-6e18750e9d48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919643264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.919643264
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.812327154
Short name T1064
Test name
Test status
Simulation time 15375814 ps
CPU time 0.77 seconds
Started Jun 22 04:50:55 PM PDT 24
Finished Jun 22 04:50:56 PM PDT 24
Peak memory 204504 kb
Host smart-0a3620d2-00fa-445a-8fe9-ccd64ed2aad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812327154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.812327154
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1548576978
Short name T1066
Test name
Test status
Simulation time 128836974 ps
CPU time 2.03 seconds
Started Jun 22 04:50:48 PM PDT 24
Finished Jun 22 04:50:51 PM PDT 24
Peak memory 216296 kb
Host smart-098fe75f-6b48-4319-9366-97b87436873b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548576978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1548576978
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3078001373
Short name T114
Test name
Test status
Simulation time 1170105834 ps
CPU time 2.97 seconds
Started Jun 22 04:50:53 PM PDT 24
Finished Jun 22 04:50:56 PM PDT 24
Peak memory 216160 kb
Host smart-1a7a002d-9b4a-4bae-847e-67e4812cf8be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078001373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3078001373
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.689539742
Short name T1018
Test name
Test status
Simulation time 3241413020 ps
CPU time 16.53 seconds
Started Jun 22 04:50:47 PM PDT 24
Finished Jun 22 04:51:05 PM PDT 24
Peak memory 216476 kb
Host smart-654bf865-5a87-48b9-9885-2c396e17cc17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689539742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.689539742
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2372581182
Short name T988
Test name
Test status
Simulation time 410051911 ps
CPU time 2.72 seconds
Started Jun 22 04:50:47 PM PDT 24
Finished Jun 22 04:50:51 PM PDT 24
Peak memory 217140 kb
Host smart-57529946-74f3-4556-ac44-4f44670bc544
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372581182 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2372581182
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.230729116
Short name T981
Test name
Test status
Simulation time 120005166 ps
CPU time 1.26 seconds
Started Jun 22 04:50:45 PM PDT 24
Finished Jun 22 04:50:47 PM PDT 24
Peak memory 207736 kb
Host smart-05b8859d-2252-4c5e-b7b1-5dc3c2ad79be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230729116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.230729116
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2960854252
Short name T1043
Test name
Test status
Simulation time 11040907 ps
CPU time 0.69 seconds
Started Jun 22 04:50:45 PM PDT 24
Finished Jun 22 04:50:47 PM PDT 24
Peak memory 204384 kb
Host smart-6572af2f-641d-4c2d-88b4-73b90fc7bbda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960854252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2960854252
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.865423555
Short name T1039
Test name
Test status
Simulation time 633897054 ps
CPU time 3.16 seconds
Started Jun 22 04:50:54 PM PDT 24
Finished Jun 22 04:50:58 PM PDT 24
Peak memory 215952 kb
Host smart-db5af884-7046-4337-acf7-e5ca080bfb3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865423555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.865423555
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3065699426
Short name T1078
Test name
Test status
Simulation time 157075104 ps
CPU time 2.05 seconds
Started Jun 22 04:50:45 PM PDT 24
Finished Jun 22 04:50:47 PM PDT 24
Peak memory 216172 kb
Host smart-a6b241b3-9884-43d2-9f66-67a23d6037de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065699426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3065699426
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3849262059
Short name T1056
Test name
Test status
Simulation time 90323406 ps
CPU time 1.66 seconds
Started Jun 22 04:50:59 PM PDT 24
Finished Jun 22 04:51:01 PM PDT 24
Peak memory 216000 kb
Host smart-3b0ad784-c3a7-4bdc-85fa-b9fbeddcaaa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849262059 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3849262059
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1428374580
Short name T993
Test name
Test status
Simulation time 46064672 ps
CPU time 1.7 seconds
Started Jun 22 04:50:55 PM PDT 24
Finished Jun 22 04:50:58 PM PDT 24
Peak memory 216004 kb
Host smart-c95e00ec-7fd6-4367-bbdd-c5d10ec7b9f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428374580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1428374580
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1013908062
Short name T975
Test name
Test status
Simulation time 39497539 ps
CPU time 0.7 seconds
Started Jun 22 04:50:56 PM PDT 24
Finished Jun 22 04:50:57 PM PDT 24
Peak memory 204324 kb
Host smart-160ffcab-3349-4fbd-9fbe-6b4b4a2f71f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013908062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1013908062
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1293888874
Short name T999
Test name
Test status
Simulation time 92185161 ps
CPU time 3.12 seconds
Started Jun 22 04:50:53 PM PDT 24
Finished Jun 22 04:50:57 PM PDT 24
Peak memory 215872 kb
Host smart-5954801a-fc63-443c-9c94-fcf20ccc4c2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293888874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1293888874
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2528963775
Short name T110
Test name
Test status
Simulation time 1272704647 ps
CPU time 5.16 seconds
Started Jun 22 04:50:58 PM PDT 24
Finished Jun 22 04:51:04 PM PDT 24
Peak memory 216112 kb
Host smart-0b79e94a-578e-4843-b7bf-fbbe4826041e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528963775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2528963775
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1953649935
Short name T996
Test name
Test status
Simulation time 481033687 ps
CPU time 1.82 seconds
Started Jun 22 04:50:52 PM PDT 24
Finished Jun 22 04:50:54 PM PDT 24
Peak memory 217096 kb
Host smart-c2ac0cdb-b500-47f3-9bbc-cadcb9462a0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953649935 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1953649935
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4043058906
Short name T127
Test name
Test status
Simulation time 225302336 ps
CPU time 2.63 seconds
Started Jun 22 04:51:00 PM PDT 24
Finished Jun 22 04:51:04 PM PDT 24
Peak memory 215968 kb
Host smart-b904eb0b-6769-4902-b08b-610ef451db69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043058906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4043058906
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2624723526
Short name T1052
Test name
Test status
Simulation time 19771389 ps
CPU time 0.7 seconds
Started Jun 22 04:50:53 PM PDT 24
Finished Jun 22 04:50:54 PM PDT 24
Peak memory 204356 kb
Host smart-32fbee33-a9b7-4851-a3a7-8b144522f213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624723526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2624723526
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3904141103
Short name T1037
Test name
Test status
Simulation time 110677521 ps
CPU time 2.97 seconds
Started Jun 22 04:50:58 PM PDT 24
Finished Jun 22 04:51:02 PM PDT 24
Peak memory 215944 kb
Host smart-7de504d7-f1ff-48d7-a0b0-1dbe8ebe62c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904141103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3904141103
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1300014018
Short name T1047
Test name
Test status
Simulation time 495519114 ps
CPU time 1.89 seconds
Started Jun 22 04:50:55 PM PDT 24
Finished Jun 22 04:50:58 PM PDT 24
Peak memory 216068 kb
Host smart-63081e76-1726-4e73-8198-06845ff1da1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300014018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1300014018
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.617744990
Short name T1062
Test name
Test status
Simulation time 209317995 ps
CPU time 14.8 seconds
Started Jun 22 04:50:38 PM PDT 24
Finished Jun 22 04:50:54 PM PDT 24
Peak memory 207716 kb
Host smart-f2985520-3956-4942-bc2c-998ea6f05ec8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617744990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.617744990
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1566646776
Short name T134
Test name
Test status
Simulation time 2442951546 ps
CPU time 12.02 seconds
Started Jun 22 04:50:30 PM PDT 24
Finished Jun 22 04:50:42 PM PDT 24
Peak memory 207704 kb
Host smart-3a02e0f4-3115-4c95-86f9-94770c2f7742
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566646776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1566646776
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3000474987
Short name T1000
Test name
Test status
Simulation time 35582074 ps
CPU time 0.96 seconds
Started Jun 22 04:50:37 PM PDT 24
Finished Jun 22 04:50:39 PM PDT 24
Peak memory 207504 kb
Host smart-3ee49dd0-a796-4c63-ad36-e4317f093b85
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000474987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3000474987
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.995387427
Short name T115
Test name
Test status
Simulation time 57327422 ps
CPU time 1.65 seconds
Started Jun 22 04:50:32 PM PDT 24
Finished Jun 22 04:50:35 PM PDT 24
Peak memory 215928 kb
Host smart-ec629198-563e-4f4e-88c7-a7fd734eac13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995387427 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.995387427
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1143323688
Short name T997
Test name
Test status
Simulation time 43385774 ps
CPU time 1.32 seconds
Started Jun 22 04:50:31 PM PDT 24
Finished Jun 22 04:50:33 PM PDT 24
Peak memory 207736 kb
Host smart-20490729-ec43-4782-ba8a-b89886b5caf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143323688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
143323688
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.383862733
Short name T970
Test name
Test status
Simulation time 14452426 ps
CPU time 0.77 seconds
Started Jun 22 04:50:30 PM PDT 24
Finished Jun 22 04:50:32 PM PDT 24
Peak memory 204348 kb
Host smart-fa44c895-05b3-4372-97c6-201a4703654c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383862733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.383862733
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1463173888
Short name T1061
Test name
Test status
Simulation time 60517792 ps
CPU time 2.07 seconds
Started Jun 22 04:50:33 PM PDT 24
Finished Jun 22 04:50:36 PM PDT 24
Peak memory 215984 kb
Host smart-72c329ae-df65-41ab-8ac8-08e70a97d449
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463173888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1463173888
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1754938410
Short name T1008
Test name
Test status
Simulation time 36352073 ps
CPU time 0.67 seconds
Started Jun 22 04:50:33 PM PDT 24
Finished Jun 22 04:50:35 PM PDT 24
Peak memory 204588 kb
Host smart-5631e5cc-d3b2-4b56-97fb-b20bcf287857
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754938410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1754938410
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1059323072
Short name T151
Test name
Test status
Simulation time 177636448 ps
CPU time 3.74 seconds
Started Jun 22 04:50:43 PM PDT 24
Finished Jun 22 04:50:48 PM PDT 24
Peak memory 215916 kb
Host smart-9fc95bee-7945-476e-961a-998a5b588cce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059323072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1059323072
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2667124617
Short name T1059
Test name
Test status
Simulation time 82632304 ps
CPU time 1.84 seconds
Started Jun 22 04:50:34 PM PDT 24
Finished Jun 22 04:50:37 PM PDT 24
Peak memory 216120 kb
Host smart-3034c7e8-bc72-4dc7-a2cc-616a181d2997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667124617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
667124617
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2775697640
Short name T102
Test name
Test status
Simulation time 195765641 ps
CPU time 13.09 seconds
Started Jun 22 04:50:39 PM PDT 24
Finished Jun 22 04:50:53 PM PDT 24
Peak memory 216412 kb
Host smart-7c00f542-ee2e-46a0-8be7-d6edbc14e37d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775697640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2775697640
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2877985298
Short name T1016
Test name
Test status
Simulation time 22061542 ps
CPU time 0.79 seconds
Started Jun 22 04:50:54 PM PDT 24
Finished Jun 22 04:50:56 PM PDT 24
Peak memory 204692 kb
Host smart-30d18dc3-3106-4d5e-95fe-fb8f3a8d33ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877985298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2877985298
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3878489419
Short name T1026
Test name
Test status
Simulation time 45819936 ps
CPU time 0.73 seconds
Started Jun 22 04:51:01 PM PDT 24
Finished Jun 22 04:51:03 PM PDT 24
Peak memory 204676 kb
Host smart-e2ba33e1-fc1f-48c4-aef2-47781da2ca10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878489419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3878489419
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1788464318
Short name T1004
Test name
Test status
Simulation time 14245397 ps
CPU time 0.72 seconds
Started Jun 22 04:50:57 PM PDT 24
Finished Jun 22 04:50:58 PM PDT 24
Peak memory 204632 kb
Host smart-998edf6c-5a34-4f4b-9904-578728b9c300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788464318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1788464318
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1648683377
Short name T1076
Test name
Test status
Simulation time 51036811 ps
CPU time 0.75 seconds
Started Jun 22 04:50:54 PM PDT 24
Finished Jun 22 04:50:55 PM PDT 24
Peak memory 204356 kb
Host smart-1a19231e-15b5-46b4-a22c-ae85511cb8dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648683377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1648683377
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2860931771
Short name T973
Test name
Test status
Simulation time 34267166 ps
CPU time 0.7 seconds
Started Jun 22 04:50:59 PM PDT 24
Finished Jun 22 04:51:00 PM PDT 24
Peak memory 204352 kb
Host smart-b756e667-cce2-40dd-a523-260e5223f2e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860931771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2860931771
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3278027675
Short name T991
Test name
Test status
Simulation time 62070335 ps
CPU time 0.76 seconds
Started Jun 22 04:50:57 PM PDT 24
Finished Jun 22 04:50:59 PM PDT 24
Peak memory 204348 kb
Host smart-8fa77baf-37a8-4d06-af0e-5f92a6bddf41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278027675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3278027675
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2164166021
Short name T1048
Test name
Test status
Simulation time 15397352 ps
CPU time 0.73 seconds
Started Jun 22 04:50:58 PM PDT 24
Finished Jun 22 04:50:59 PM PDT 24
Peak memory 204676 kb
Host smart-9d697863-950d-456d-b503-7f567bff7369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164166021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2164166021
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.452099278
Short name T982
Test name
Test status
Simulation time 15634693 ps
CPU time 0.71 seconds
Started Jun 22 04:50:57 PM PDT 24
Finished Jun 22 04:50:58 PM PDT 24
Peak memory 204240 kb
Host smart-021a168d-aa43-4226-bcd2-b4ebc5d1bac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452099278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.452099278
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.232070366
Short name T986
Test name
Test status
Simulation time 11919666 ps
CPU time 0.75 seconds
Started Jun 22 04:50:53 PM PDT 24
Finished Jun 22 04:50:55 PM PDT 24
Peak memory 204248 kb
Host smart-2f89ef26-fa36-45e0-9a87-66da22b49085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232070366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.232070366
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.582129042
Short name T1036
Test name
Test status
Simulation time 17596148 ps
CPU time 0.76 seconds
Started Jun 22 04:50:55 PM PDT 24
Finished Jun 22 04:50:56 PM PDT 24
Peak memory 204348 kb
Host smart-34725e34-8579-4010-b545-e45c77ac7f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582129042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.582129042
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1381315272
Short name T133
Test name
Test status
Simulation time 1247653932 ps
CPU time 14.74 seconds
Started Jun 22 04:50:32 PM PDT 24
Finished Jun 22 04:50:47 PM PDT 24
Peak memory 215976 kb
Host smart-259deaa2-5711-4499-88bf-3149721b5cf3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381315272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1381315272
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.556470152
Short name T998
Test name
Test status
Simulation time 8638748611 ps
CPU time 13.3 seconds
Started Jun 22 04:50:33 PM PDT 24
Finished Jun 22 04:50:47 PM PDT 24
Peak memory 207828 kb
Host smart-cbedb097-6069-40e9-bf81-b30214198e2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556470152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.556470152
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2165919241
Short name T89
Test name
Test status
Simulation time 179320793 ps
CPU time 1.4 seconds
Started Jun 22 04:50:44 PM PDT 24
Finished Jun 22 04:50:45 PM PDT 24
Peak memory 207700 kb
Host smart-eae10dc5-374c-40db-83ae-81b07f4d299a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165919241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2165919241
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1722213794
Short name T120
Test name
Test status
Simulation time 90910950 ps
CPU time 2.73 seconds
Started Jun 22 04:50:35 PM PDT 24
Finished Jun 22 04:50:39 PM PDT 24
Peak memory 217616 kb
Host smart-fbe1269b-01c2-4f98-b568-b741185f4b6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722213794 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1722213794
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1466489572
Short name T1022
Test name
Test status
Simulation time 161812374 ps
CPU time 1.37 seconds
Started Jun 22 04:50:32 PM PDT 24
Finished Jun 22 04:50:35 PM PDT 24
Peak memory 215968 kb
Host smart-29e1a45f-c68f-464d-988d-bacff154005c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466489572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
466489572
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3247870670
Short name T978
Test name
Test status
Simulation time 12434510 ps
CPU time 0.7 seconds
Started Jun 22 04:50:32 PM PDT 24
Finished Jun 22 04:50:33 PM PDT 24
Peak memory 204672 kb
Host smart-3a48b2b1-420a-4ad1-bb6a-ef589aee7519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247870670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
247870670
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4278678444
Short name T1072
Test name
Test status
Simulation time 48226272 ps
CPU time 1.77 seconds
Started Jun 22 04:50:33 PM PDT 24
Finished Jun 22 04:50:36 PM PDT 24
Peak memory 215908 kb
Host smart-7e6c63df-be2f-4ce6-af44-709162722b51
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278678444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4278678444
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2792307722
Short name T971
Test name
Test status
Simulation time 18869737 ps
CPU time 0.65 seconds
Started Jun 22 04:50:34 PM PDT 24
Finished Jun 22 04:50:36 PM PDT 24
Peak memory 204296 kb
Host smart-eb21ded4-31a5-4918-a9b7-27791d6db2ca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792307722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2792307722
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4194803467
Short name T1032
Test name
Test status
Simulation time 1242897835 ps
CPU time 4.27 seconds
Started Jun 22 04:50:31 PM PDT 24
Finished Jun 22 04:50:36 PM PDT 24
Peak memory 215880 kb
Host smart-72c1dd59-3d17-42ba-9f15-e13a23b3f58b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194803467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.4194803467
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3388524773
Short name T112
Test name
Test status
Simulation time 122741176 ps
CPU time 3.95 seconds
Started Jun 22 04:50:42 PM PDT 24
Finished Jun 22 04:50:47 PM PDT 24
Peak memory 216012 kb
Host smart-9aa587d9-c538-4049-8b6d-31ff7b3e29e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388524773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
388524773
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3540358424
Short name T965
Test name
Test status
Simulation time 17428316 ps
CPU time 0.75 seconds
Started Jun 22 04:51:01 PM PDT 24
Finished Jun 22 04:51:02 PM PDT 24
Peak memory 204360 kb
Host smart-dece8938-b159-4118-b91a-33e7129f7b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540358424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3540358424
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1412714438
Short name T1009
Test name
Test status
Simulation time 34045762 ps
CPU time 0.72 seconds
Started Jun 22 04:50:53 PM PDT 24
Finished Jun 22 04:50:55 PM PDT 24
Peak memory 204628 kb
Host smart-478b7fa4-a303-4f82-8ad0-2746ae244704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412714438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1412714438
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2225921237
Short name T990
Test name
Test status
Simulation time 16710120 ps
CPU time 0.77 seconds
Started Jun 22 04:51:05 PM PDT 24
Finished Jun 22 04:51:06 PM PDT 24
Peak memory 204496 kb
Host smart-09fd65e5-4853-4ba3-b10e-daf921911a6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225921237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2225921237
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.625919547
Short name T1055
Test name
Test status
Simulation time 14471854 ps
CPU time 0.79 seconds
Started Jun 22 04:51:01 PM PDT 24
Finished Jun 22 04:51:03 PM PDT 24
Peak memory 204352 kb
Host smart-b83efa37-4bd4-4b78-adb3-f887c1ff956f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625919547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.625919547
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2477724914
Short name T980
Test name
Test status
Simulation time 17078082 ps
CPU time 0.77 seconds
Started Jun 22 04:51:04 PM PDT 24
Finished Jun 22 04:51:06 PM PDT 24
Peak memory 204344 kb
Host smart-ddce41c8-8534-4c96-8182-c1d80724d03e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477724914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2477724914
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1385973446
Short name T1063
Test name
Test status
Simulation time 15425006 ps
CPU time 0.74 seconds
Started Jun 22 04:51:00 PM PDT 24
Finished Jun 22 04:51:01 PM PDT 24
Peak memory 204344 kb
Host smart-fd50febc-b0a8-44b2-ad3c-21e358070151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385973446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1385973446
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2288625248
Short name T977
Test name
Test status
Simulation time 13993842 ps
CPU time 0.7 seconds
Started Jun 22 04:51:02 PM PDT 24
Finished Jun 22 04:51:03 PM PDT 24
Peak memory 204344 kb
Host smart-1b804d02-2965-4ab6-88be-cb82b4c574b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288625248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2288625248
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.439561807
Short name T1029
Test name
Test status
Simulation time 11488511 ps
CPU time 0.74 seconds
Started Jun 22 04:51:01 PM PDT 24
Finished Jun 22 04:51:02 PM PDT 24
Peak memory 204264 kb
Host smart-14a749d6-f13d-46a2-98c5-cdd2dd51b7d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439561807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.439561807
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.601447996
Short name T1025
Test name
Test status
Simulation time 44342466 ps
CPU time 0.81 seconds
Started Jun 22 04:51:02 PM PDT 24
Finished Jun 22 04:51:03 PM PDT 24
Peak memory 204252 kb
Host smart-17eb30da-3962-4547-a35a-947c12d2fd8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601447996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.601447996
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3866610650
Short name T968
Test name
Test status
Simulation time 18864491 ps
CPU time 0.68 seconds
Started Jun 22 04:51:06 PM PDT 24
Finished Jun 22 04:51:07 PM PDT 24
Peak memory 204500 kb
Host smart-c86c3b02-4d6e-4941-ab43-87b89909ca07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866610650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3866610650
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4150763749
Short name T1038
Test name
Test status
Simulation time 205932972 ps
CPU time 7.92 seconds
Started Jun 22 04:50:32 PM PDT 24
Finished Jun 22 04:50:41 PM PDT 24
Peak memory 207740 kb
Host smart-522cbabd-6269-4e6b-a9c5-a4c837671b97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150763749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4150763749
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3042124288
Short name T974
Test name
Test status
Simulation time 1225449670 ps
CPU time 25.77 seconds
Started Jun 22 04:50:33 PM PDT 24
Finished Jun 22 04:51:00 PM PDT 24
Peak memory 207724 kb
Host smart-2564d02c-6475-4ee7-b666-ebed517f79b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042124288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3042124288
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2137915788
Short name T90
Test name
Test status
Simulation time 79386349 ps
CPU time 0.94 seconds
Started Jun 22 04:50:34 PM PDT 24
Finished Jun 22 04:50:36 PM PDT 24
Peak memory 207480 kb
Host smart-79e49e6d-b42e-44c5-95e2-e4426e58c80e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137915788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2137915788
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2938390492
Short name T992
Test name
Test status
Simulation time 52799101 ps
CPU time 1.58 seconds
Started Jun 22 04:50:46 PM PDT 24
Finished Jun 22 04:50:49 PM PDT 24
Peak memory 215956 kb
Host smart-a7816bf2-1d36-447a-b568-5eaef84a40f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938390492 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2938390492
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4219183916
Short name T1044
Test name
Test status
Simulation time 116788991 ps
CPU time 1.19 seconds
Started Jun 22 04:50:43 PM PDT 24
Finished Jun 22 04:50:45 PM PDT 24
Peak memory 207772 kb
Host smart-4aaf19ee-982d-4214-982c-c6fe038d09d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219183916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
219183916
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3093234271
Short name T1031
Test name
Test status
Simulation time 52399338 ps
CPU time 0.76 seconds
Started Jun 22 04:50:34 PM PDT 24
Finished Jun 22 04:50:36 PM PDT 24
Peak memory 204236 kb
Host smart-9a28a333-f09c-44a2-9a77-3c31bba978c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093234271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
093234271
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3665537495
Short name T1011
Test name
Test status
Simulation time 126467702 ps
CPU time 2.04 seconds
Started Jun 22 04:50:32 PM PDT 24
Finished Jun 22 04:50:35 PM PDT 24
Peak memory 215940 kb
Host smart-7f2bfaf4-3430-449c-942a-ea37f1176e8a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665537495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3665537495
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1605154213
Short name T984
Test name
Test status
Simulation time 92052226 ps
CPU time 0.63 seconds
Started Jun 22 04:50:35 PM PDT 24
Finished Jun 22 04:50:36 PM PDT 24
Peak memory 204196 kb
Host smart-3180617d-644b-4d5f-9eb5-b334b69cbc8b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605154213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1605154213
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.433830291
Short name T1005
Test name
Test status
Simulation time 465555530 ps
CPU time 2.96 seconds
Started Jun 22 04:50:48 PM PDT 24
Finished Jun 22 04:50:52 PM PDT 24
Peak memory 215940 kb
Host smart-fbd7e797-2209-4cfd-a128-7078a51bc864
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433830291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.433830291
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2513664009
Short name T1065
Test name
Test status
Simulation time 225038475 ps
CPU time 3.95 seconds
Started Jun 22 04:50:33 PM PDT 24
Finished Jun 22 04:50:38 PM PDT 24
Peak memory 217232 kb
Host smart-d7982085-7515-473f-8dd3-fc5e7240afb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513664009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
513664009
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2423913901
Short name T185
Test name
Test status
Simulation time 378895400 ps
CPU time 13.08 seconds
Started Jun 22 04:50:31 PM PDT 24
Finished Jun 22 04:50:45 PM PDT 24
Peak memory 215836 kb
Host smart-df947a26-c629-4e3d-80c2-b002463582b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423913901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2423913901
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3518991523
Short name T1010
Test name
Test status
Simulation time 22907895 ps
CPU time 0.74 seconds
Started Jun 22 04:51:02 PM PDT 24
Finished Jun 22 04:51:04 PM PDT 24
Peak memory 204568 kb
Host smart-729f7923-9d04-4c46-9891-52610cdd75c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518991523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3518991523
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2312716521
Short name T987
Test name
Test status
Simulation time 11632710 ps
CPU time 0.77 seconds
Started Jun 22 04:51:03 PM PDT 24
Finished Jun 22 04:51:05 PM PDT 24
Peak memory 204276 kb
Host smart-4b0c9c03-cd2f-4fce-8565-7fd5f2c10ad8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312716521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2312716521
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.886371778
Short name T1015
Test name
Test status
Simulation time 38276642 ps
CPU time 0.71 seconds
Started Jun 22 04:51:02 PM PDT 24
Finished Jun 22 04:51:04 PM PDT 24
Peak memory 204352 kb
Host smart-a3cccdcd-104c-4586-984c-5e8c2f5900dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886371778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.886371778
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3277627560
Short name T1030
Test name
Test status
Simulation time 56931523 ps
CPU time 0.74 seconds
Started Jun 22 04:50:59 PM PDT 24
Finished Jun 22 04:51:00 PM PDT 24
Peak memory 204656 kb
Host smart-0aa837cb-ad99-45a6-9a8b-5c38fc66a015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277627560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3277627560
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1120077760
Short name T972
Test name
Test status
Simulation time 12579726 ps
CPU time 0.74 seconds
Started Jun 22 04:51:01 PM PDT 24
Finished Jun 22 04:51:02 PM PDT 24
Peak memory 204356 kb
Host smart-013e10f4-3f83-48c0-8096-dc6a6dd14e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120077760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1120077760
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3143204401
Short name T1074
Test name
Test status
Simulation time 18106550 ps
CPU time 0.75 seconds
Started Jun 22 04:50:59 PM PDT 24
Finished Jun 22 04:51:00 PM PDT 24
Peak memory 204668 kb
Host smart-c5126eb6-0f64-43e9-9d39-a7f684b8fdd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143204401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3143204401
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.710448613
Short name T1067
Test name
Test status
Simulation time 40422917 ps
CPU time 0.74 seconds
Started Jun 22 04:51:03 PM PDT 24
Finished Jun 22 04:51:05 PM PDT 24
Peak memory 204284 kb
Host smart-4c6b5f93-6ba5-4890-9734-5357ba8c867d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710448613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.710448613
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2251871426
Short name T995
Test name
Test status
Simulation time 23137561 ps
CPU time 0.74 seconds
Started Jun 22 04:51:00 PM PDT 24
Finished Jun 22 04:51:01 PM PDT 24
Peak memory 204356 kb
Host smart-38c3d221-91af-4aa2-a5ac-7c69b96efe2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251871426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2251871426
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.204708742
Short name T969
Test name
Test status
Simulation time 38205163 ps
CPU time 0.75 seconds
Started Jun 22 04:51:04 PM PDT 24
Finished Jun 22 04:51:06 PM PDT 24
Peak memory 204548 kb
Host smart-dd13bebe-88c4-45b9-a193-2dbd085b5433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204708742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.204708742
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2616446462
Short name T994
Test name
Test status
Simulation time 15116056 ps
CPU time 0.73 seconds
Started Jun 22 04:51:01 PM PDT 24
Finished Jun 22 04:51:02 PM PDT 24
Peak memory 204352 kb
Host smart-1411df5e-1898-4cbc-bbf0-e79049952ca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616446462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2616446462
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4006042108
Short name T121
Test name
Test status
Simulation time 134356822 ps
CPU time 3.72 seconds
Started Jun 22 04:50:43 PM PDT 24
Finished Jun 22 04:50:47 PM PDT 24
Peak memory 217444 kb
Host smart-20422eb1-7ec2-4471-9948-3394a0df64f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006042108 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4006042108
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1780551807
Short name T1033
Test name
Test status
Simulation time 268318827 ps
CPU time 2.6 seconds
Started Jun 22 04:50:42 PM PDT 24
Finished Jun 22 04:50:46 PM PDT 24
Peak memory 215932 kb
Host smart-a7f07000-8c81-48f4-a2cc-8cd0391e3d9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780551807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
780551807
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1799798501
Short name T1020
Test name
Test status
Simulation time 14576255 ps
CPU time 0.77 seconds
Started Jun 22 04:50:36 PM PDT 24
Finished Jun 22 04:50:38 PM PDT 24
Peak memory 204352 kb
Host smart-ea7f2d86-a505-41d3-8888-10cd246c1ebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799798501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
799798501
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1372022940
Short name T976
Test name
Test status
Simulation time 29374852 ps
CPU time 1.7 seconds
Started Jun 22 04:50:45 PM PDT 24
Finished Jun 22 04:50:48 PM PDT 24
Peak memory 215920 kb
Host smart-3d89d4ab-aa81-4d6d-82b6-a28e7d95908a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372022940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1372022940
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.459729136
Short name T1079
Test name
Test status
Simulation time 202317220 ps
CPU time 5.41 seconds
Started Jun 22 04:50:43 PM PDT 24
Finished Jun 22 04:50:49 PM PDT 24
Peak memory 217084 kb
Host smart-2caa3e4a-e1b6-4f90-a643-198521e2a979
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459729136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.459729136
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.998480676
Short name T1077
Test name
Test status
Simulation time 649530449 ps
CPU time 6.8 seconds
Started Jun 22 04:50:42 PM PDT 24
Finished Jun 22 04:50:50 PM PDT 24
Peak memory 215928 kb
Host smart-f5e3d0b5-a1f9-4c43-a307-d8fb0c71b766
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998480676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.998480676
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3799838883
Short name T123
Test name
Test status
Simulation time 78534399 ps
CPU time 2.75 seconds
Started Jun 22 04:50:39 PM PDT 24
Finished Jun 22 04:50:42 PM PDT 24
Peak memory 217688 kb
Host smart-4751ffe4-39e4-4308-9168-8713d4e5df5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799838883 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3799838883
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.888761449
Short name T985
Test name
Test status
Simulation time 388728890 ps
CPU time 2.14 seconds
Started Jun 22 04:50:47 PM PDT 24
Finished Jun 22 04:50:50 PM PDT 24
Peak memory 215972 kb
Host smart-15068dd9-d4a3-4cc8-a43f-5efa6e4294c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888761449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.888761449
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1008512639
Short name T979
Test name
Test status
Simulation time 15046606 ps
CPU time 0.75 seconds
Started Jun 22 04:50:41 PM PDT 24
Finished Jun 22 04:50:42 PM PDT 24
Peak memory 204340 kb
Host smart-0805f70a-a3c5-43d1-9613-0251a296ec69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008512639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
008512639
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3370840475
Short name T1023
Test name
Test status
Simulation time 157930652 ps
CPU time 4.16 seconds
Started Jun 22 04:50:47 PM PDT 24
Finished Jun 22 04:50:52 PM PDT 24
Peak memory 215940 kb
Host smart-6a36e082-5e46-4254-b26a-80dd42f49c64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370840475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3370840475
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1177383054
Short name T1071
Test name
Test status
Simulation time 20038931 ps
CPU time 1.45 seconds
Started Jun 22 04:50:42 PM PDT 24
Finished Jun 22 04:50:44 PM PDT 24
Peak memory 216240 kb
Host smart-91b6ab43-64a8-48fe-8916-93370331cc07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177383054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
177383054
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2016075843
Short name T182
Test name
Test status
Simulation time 427298390 ps
CPU time 6.61 seconds
Started Jun 22 04:50:48 PM PDT 24
Finished Jun 22 04:50:56 PM PDT 24
Peak memory 216468 kb
Host smart-efc1b7dd-ab74-4005-a192-c36a65a3a605
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016075843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2016075843
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2921321716
Short name T1080
Test name
Test status
Simulation time 41906578 ps
CPU time 2.87 seconds
Started Jun 22 04:50:41 PM PDT 24
Finished Jun 22 04:50:45 PM PDT 24
Peak memory 217468 kb
Host smart-f3162249-a069-465c-9254-ce2bbe478196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921321716 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2921321716
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2936623956
Short name T132
Test name
Test status
Simulation time 46526292 ps
CPU time 2.57 seconds
Started Jun 22 04:50:46 PM PDT 24
Finished Jun 22 04:50:50 PM PDT 24
Peak memory 216004 kb
Host smart-59833f92-2419-4595-b5a7-966467cd207b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936623956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
936623956
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3115078697
Short name T1028
Test name
Test status
Simulation time 17875148 ps
CPU time 0.79 seconds
Started Jun 22 04:50:39 PM PDT 24
Finished Jun 22 04:50:41 PM PDT 24
Peak memory 204216 kb
Host smart-e7194357-b3d7-4da2-a560-e22c0c3e8973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115078697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
115078697
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1679046705
Short name T1081
Test name
Test status
Simulation time 408275068 ps
CPU time 4.53 seconds
Started Jun 22 04:50:48 PM PDT 24
Finished Jun 22 04:50:53 PM PDT 24
Peak memory 215908 kb
Host smart-9eb43140-7ca9-4253-9b9c-4c5465ad7830
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679046705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1679046705
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2722641746
Short name T107
Test name
Test status
Simulation time 618209385 ps
CPU time 4.21 seconds
Started Jun 22 04:50:38 PM PDT 24
Finished Jun 22 04:50:43 PM PDT 24
Peak memory 215980 kb
Host smart-f583f644-3083-4dfd-b666-82652b9d2407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722641746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
722641746
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3915717915
Short name T180
Test name
Test status
Simulation time 426853199 ps
CPU time 6.35 seconds
Started Jun 22 04:50:39 PM PDT 24
Finished Jun 22 04:50:46 PM PDT 24
Peak memory 215964 kb
Host smart-701c434c-e6ea-476d-bbf7-000377486e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915717915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3915717915
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3177325707
Short name T103
Test name
Test status
Simulation time 264779475 ps
CPU time 4.02 seconds
Started Jun 22 04:50:38 PM PDT 24
Finished Jun 22 04:50:43 PM PDT 24
Peak memory 217768 kb
Host smart-3a49f30b-d4b6-4dbf-abb0-bef973539366
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177325707 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3177325707
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1841084124
Short name T125
Test name
Test status
Simulation time 114658611 ps
CPU time 1.84 seconds
Started Jun 22 04:50:46 PM PDT 24
Finished Jun 22 04:50:49 PM PDT 24
Peak memory 215944 kb
Host smart-5d719474-5935-4ee4-b8fb-f47ccc207f89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841084124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
841084124
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3976221196
Short name T1017
Test name
Test status
Simulation time 23709605 ps
CPU time 0.72 seconds
Started Jun 22 04:50:40 PM PDT 24
Finished Jun 22 04:50:41 PM PDT 24
Peak memory 204364 kb
Host smart-a187fc7f-882d-45cc-af07-37c6161b2210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976221196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
976221196
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1838140764
Short name T967
Test name
Test status
Simulation time 28068110 ps
CPU time 1.72 seconds
Started Jun 22 04:51:41 PM PDT 24
Finished Jun 22 04:51:43 PM PDT 24
Peak memory 215936 kb
Host smart-e7037af5-3b04-45ff-bb5b-1aae715015f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838140764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1838140764
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2373742818
Short name T186
Test name
Test status
Simulation time 786175093 ps
CPU time 12.67 seconds
Started Jun 22 04:50:37 PM PDT 24
Finished Jun 22 04:50:51 PM PDT 24
Peak memory 216140 kb
Host smart-98a35002-b611-4ffd-86bd-2a6a8e244c03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373742818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2373742818
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3434488781
Short name T117
Test name
Test status
Simulation time 54111704 ps
CPU time 3.95 seconds
Started Jun 22 04:50:51 PM PDT 24
Finished Jun 22 04:50:55 PM PDT 24
Peak memory 218788 kb
Host smart-8aa182fb-746e-4917-9192-7a64ec45d6fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434488781 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3434488781
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.235723971
Short name T126
Test name
Test status
Simulation time 1271530431 ps
CPU time 2.61 seconds
Started Jun 22 04:50:39 PM PDT 24
Finished Jun 22 04:50:42 PM PDT 24
Peak memory 215792 kb
Host smart-984e8d54-4517-4fd3-bdf4-bd1b813b7b9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235723971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.235723971
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4145940196
Short name T1075
Test name
Test status
Simulation time 47814816 ps
CPU time 0.78 seconds
Started Jun 22 04:50:39 PM PDT 24
Finished Jun 22 04:50:41 PM PDT 24
Peak memory 204672 kb
Host smart-540925b0-6b24-46c5-8d79-8f9ecc7df31c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145940196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4
145940196
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3646735562
Short name T158
Test name
Test status
Simulation time 390861912 ps
CPU time 4.1 seconds
Started Jun 22 04:50:45 PM PDT 24
Finished Jun 22 04:50:50 PM PDT 24
Peak memory 215924 kb
Host smart-74e918ec-88f9-40c4-8738-9a072f024424
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646735562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3646735562
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2512676150
Short name T109
Test name
Test status
Simulation time 126532521 ps
CPU time 2.2 seconds
Started Jun 22 04:50:40 PM PDT 24
Finished Jun 22 04:50:43 PM PDT 24
Peak memory 216124 kb
Host smart-28825de7-6d89-41ce-9169-192212be93f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512676150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
512676150
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1722495747
Short name T188
Test name
Test status
Simulation time 831987135 ps
CPU time 21.95 seconds
Started Jun 22 04:50:48 PM PDT 24
Finished Jun 22 04:51:11 PM PDT 24
Peak memory 215980 kb
Host smart-2a64251f-42c3-44aa-b27e-9f7bec20de9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722495747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1722495747
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3800293365
Short name T602
Test name
Test status
Simulation time 78511838 ps
CPU time 0.74 seconds
Started Jun 22 06:09:30 PM PDT 24
Finished Jun 22 06:09:31 PM PDT 24
Peak memory 205536 kb
Host smart-7fd10be7-4068-4f6d-af40-ae63a6c844a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800293365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
800293365
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1617632982
Short name T939
Test name
Test status
Simulation time 1048629949 ps
CPU time 10.2 seconds
Started Jun 22 06:09:27 PM PDT 24
Finished Jun 22 06:09:38 PM PDT 24
Peak memory 232896 kb
Host smart-474d722c-8441-48b6-9798-e6734c939be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617632982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1617632982
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2034504560
Short name T933
Test name
Test status
Simulation time 128226104 ps
CPU time 0.78 seconds
Started Jun 22 06:09:22 PM PDT 24
Finished Jun 22 06:09:23 PM PDT 24
Peak memory 206044 kb
Host smart-f1f39311-9e20-4e94-a996-3b9334134c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034504560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2034504560
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.51297567
Short name T913
Test name
Test status
Simulation time 5943533261 ps
CPU time 45.84 seconds
Started Jun 22 06:09:21 PM PDT 24
Finished Jun 22 06:10:07 PM PDT 24
Peak memory 257044 kb
Host smart-a54dd401-4955-464a-9461-63e0ae6eb78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51297567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.51297567
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.4147434692
Short name T326
Test name
Test status
Simulation time 115421747919 ps
CPU time 240.06 seconds
Started Jun 22 06:09:30 PM PDT 24
Finished Jun 22 06:13:31 PM PDT 24
Peak memory 252468 kb
Host smart-85bc5084-cf15-4f50-bae3-6c506943f47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147434692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.4147434692
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1231080936
Short name T489
Test name
Test status
Simulation time 393606329 ps
CPU time 6.32 seconds
Started Jun 22 06:09:28 PM PDT 24
Finished Jun 22 06:09:35 PM PDT 24
Peak memory 236540 kb
Host smart-d532ba92-b76c-463e-9871-830558250513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231080936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1231080936
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4216299435
Short name T465
Test name
Test status
Simulation time 29446687 ps
CPU time 2.45 seconds
Started Jun 22 06:09:23 PM PDT 24
Finished Jun 22 06:09:26 PM PDT 24
Peak memory 232560 kb
Host smart-97735b80-396a-4ce9-95e8-241ed2d8eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216299435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4216299435
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1174993556
Short name T902
Test name
Test status
Simulation time 5394439842 ps
CPU time 18.69 seconds
Started Jun 22 06:09:21 PM PDT 24
Finished Jun 22 06:09:41 PM PDT 24
Peak memory 233024 kb
Host smart-b8e15e86-3cdc-4692-95d4-d4bf15be4072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174993556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1174993556
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.699937925
Short name T845
Test name
Test status
Simulation time 2042852822 ps
CPU time 10.97 seconds
Started Jun 22 06:09:22 PM PDT 24
Finished Jun 22 06:09:33 PM PDT 24
Peak memory 238376 kb
Host smart-9758568e-a5ac-4479-9e6d-94dd63990f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699937925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
699937925
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1437676085
Short name T372
Test name
Test status
Simulation time 7940180262 ps
CPU time 10.36 seconds
Started Jun 22 06:09:20 PM PDT 24
Finished Jun 22 06:09:31 PM PDT 24
Peak memory 224708 kb
Host smart-f288141d-7fec-41fb-bef5-406119d11dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437676085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1437676085
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.4140557270
Short name T462
Test name
Test status
Simulation time 1080610236 ps
CPU time 13.61 seconds
Started Jun 22 06:09:27 PM PDT 24
Finished Jun 22 06:09:41 PM PDT 24
Peak memory 223356 kb
Host smart-350f9583-e782-4bbd-bc27-d81ee7450950
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4140557270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.4140557270
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.950174120
Short name T405
Test name
Test status
Simulation time 1676403492 ps
CPU time 16.36 seconds
Started Jun 22 06:09:22 PM PDT 24
Finished Jun 22 06:09:39 PM PDT 24
Peak memory 219728 kb
Host smart-d1a0f037-4b76-4f8e-b9ac-1617a0b30c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950174120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.950174120
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1033588484
Short name T349
Test name
Test status
Simulation time 1960434552 ps
CPU time 6.85 seconds
Started Jun 22 06:09:21 PM PDT 24
Finished Jun 22 06:09:28 PM PDT 24
Peak memory 216372 kb
Host smart-9d324a46-9ba2-4ec0-a93e-43a54d6a428e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033588484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1033588484
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2146393492
Short name T138
Test name
Test status
Simulation time 64068982 ps
CPU time 0.82 seconds
Started Jun 22 06:09:24 PM PDT 24
Finished Jun 22 06:09:26 PM PDT 24
Peak memory 206712 kb
Host smart-b337b0fb-36ba-4d5e-877b-24470295025f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146393492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2146393492
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3335462872
Short name T765
Test name
Test status
Simulation time 35279269 ps
CPU time 0.79 seconds
Started Jun 22 06:09:30 PM PDT 24
Finished Jun 22 06:09:32 PM PDT 24
Peak memory 206068 kb
Host smart-bcf520b1-0cba-416d-a738-46aec3d633fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335462872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3335462872
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1009768282
Short name T348
Test name
Test status
Simulation time 265855280 ps
CPU time 2.52 seconds
Started Jun 22 06:09:22 PM PDT 24
Finished Jun 22 06:09:25 PM PDT 24
Peak memory 234300 kb
Host smart-a1648d50-7161-4bcb-a3c5-728b04ea46ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009768282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1009768282
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1433461646
Short name T729
Test name
Test status
Simulation time 44464464 ps
CPU time 0.74 seconds
Started Jun 22 06:09:31 PM PDT 24
Finished Jun 22 06:09:32 PM PDT 24
Peak memory 205836 kb
Host smart-a00f6940-2038-4d71-b82d-8206277cbaa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433461646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
433461646
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1839638954
Short name T252
Test name
Test status
Simulation time 1168170527 ps
CPU time 4.53 seconds
Started Jun 22 06:09:34 PM PDT 24
Finished Jun 22 06:09:39 PM PDT 24
Peak memory 232692 kb
Host smart-fc9dd4be-ae6c-4bcb-8f9b-0c9b97f93eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839638954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1839638954
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3404309063
Short name T910
Test name
Test status
Simulation time 38077810 ps
CPU time 0.87 seconds
Started Jun 22 06:09:30 PM PDT 24
Finished Jun 22 06:09:32 PM PDT 24
Peak memory 206760 kb
Host smart-288f143b-7b10-452a-b521-a0d811f9abf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404309063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3404309063
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3445475029
Short name T293
Test name
Test status
Simulation time 4393760309 ps
CPU time 42.66 seconds
Started Jun 22 06:09:31 PM PDT 24
Finished Jun 22 06:10:14 PM PDT 24
Peak memory 248760 kb
Host smart-2e4e8849-1e2a-4121-8a2f-7b0ad4a8b451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445475029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3445475029
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2157737357
Short name T712
Test name
Test status
Simulation time 24315685733 ps
CPU time 226.83 seconds
Started Jun 22 06:09:29 PM PDT 24
Finished Jun 22 06:13:17 PM PDT 24
Peak memory 253256 kb
Host smart-efeaeeab-6908-4a24-91b8-93128eb9ea2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157737357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2157737357
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2596943856
Short name T227
Test name
Test status
Simulation time 3606928315 ps
CPU time 62.39 seconds
Started Jun 22 06:09:32 PM PDT 24
Finished Jun 22 06:10:35 PM PDT 24
Peak memory 239724 kb
Host smart-008482ce-30d5-4d36-8fd3-8f34dfed0741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596943856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2596943856
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2096861880
Short name T918
Test name
Test status
Simulation time 7790210834 ps
CPU time 21.84 seconds
Started Jun 22 06:09:29 PM PDT 24
Finished Jun 22 06:09:52 PM PDT 24
Peak memory 224744 kb
Host smart-7fef73fe-0fe9-4aec-aa13-04fd09a44f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096861880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2096861880
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.426840744
Short name T212
Test name
Test status
Simulation time 4252935783 ps
CPU time 12.67 seconds
Started Jun 22 06:09:28 PM PDT 24
Finished Jun 22 06:09:42 PM PDT 24
Peak memory 233016 kb
Host smart-6dd14a1c-b2bf-400b-96ae-5ef2417d6587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426840744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.426840744
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2902574616
Short name T872
Test name
Test status
Simulation time 13541855646 ps
CPU time 12.69 seconds
Started Jun 22 06:09:31 PM PDT 24
Finished Jun 22 06:09:45 PM PDT 24
Peak memory 225016 kb
Host smart-aceea07a-ae09-4e86-aa22-5ba955bd4a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902574616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2902574616
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2191495955
Short name T378
Test name
Test status
Simulation time 308872878 ps
CPU time 6.19 seconds
Started Jun 22 06:09:30 PM PDT 24
Finished Jun 22 06:09:37 PM PDT 24
Peak memory 232860 kb
Host smart-475d06ac-aa7a-4fc7-a2fc-6e089fdaa9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191495955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2191495955
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4084301059
Short name T498
Test name
Test status
Simulation time 2659682106 ps
CPU time 8.34 seconds
Started Jun 22 06:09:31 PM PDT 24
Finished Jun 22 06:09:40 PM PDT 24
Peak memory 223312 kb
Host smart-af400667-8c63-482c-a328-685104c8c8a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4084301059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4084301059
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1811128837
Short name T81
Test name
Test status
Simulation time 162783297 ps
CPU time 1.2 seconds
Started Jun 22 06:09:27 PM PDT 24
Finished Jun 22 06:09:29 PM PDT 24
Peak memory 235492 kb
Host smart-cd110c61-c483-476f-9f9e-82395dfcaf12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811128837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1811128837
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3064841519
Short name T161
Test name
Test status
Simulation time 10021776552 ps
CPU time 38.43 seconds
Started Jun 22 06:09:31 PM PDT 24
Finished Jun 22 06:10:10 PM PDT 24
Peak memory 241224 kb
Host smart-9fa1ea4c-e6e2-4e7e-b370-d10d1ae15b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064841519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3064841519
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.868069019
Short name T432
Test name
Test status
Simulation time 2752718242 ps
CPU time 7.76 seconds
Started Jun 22 06:09:21 PM PDT 24
Finished Jun 22 06:09:29 PM PDT 24
Peak memory 219804 kb
Host smart-374bcbd8-2059-4c6f-b255-f3487e08bbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868069019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.868069019
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.33289147
Short name T814
Test name
Test status
Simulation time 2576821077 ps
CPU time 5.78 seconds
Started Jun 22 06:09:30 PM PDT 24
Finished Jun 22 06:09:36 PM PDT 24
Peak memory 216488 kb
Host smart-a3091a7c-7ea6-41e5-a2a1-5652bd7a7fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33289147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.33289147
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3948862013
Short name T443
Test name
Test status
Simulation time 551056563 ps
CPU time 6.22 seconds
Started Jun 22 06:09:31 PM PDT 24
Finished Jun 22 06:09:38 PM PDT 24
Peak memory 216404 kb
Host smart-de8a4752-57f1-4967-bc3d-dd53376df9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948862013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3948862013
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.876420279
Short name T528
Test name
Test status
Simulation time 30028244 ps
CPU time 0.67 seconds
Started Jun 22 06:09:29 PM PDT 24
Finished Jun 22 06:09:30 PM PDT 24
Peak memory 205688 kb
Host smart-e58ff01e-ce5f-4470-8ef9-db329ec5022d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876420279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.876420279
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2752361246
Short name T381
Test name
Test status
Simulation time 73958975 ps
CPU time 2.58 seconds
Started Jun 22 06:09:29 PM PDT 24
Finished Jun 22 06:09:33 PM PDT 24
Peak memory 232676 kb
Host smart-855ac6bb-201f-4cc3-8cdc-1c70065cfcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752361246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2752361246
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1599334899
Short name T644
Test name
Test status
Simulation time 15793256 ps
CPU time 0.8 seconds
Started Jun 22 06:10:04 PM PDT 24
Finished Jun 22 06:10:05 PM PDT 24
Peak memory 204900 kb
Host smart-b846bd9d-34f5-410d-8694-e8e2ff098e25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599334899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1599334899
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.426176078
Short name T511
Test name
Test status
Simulation time 119391177 ps
CPU time 3.11 seconds
Started Jun 22 06:10:01 PM PDT 24
Finished Jun 22 06:10:05 PM PDT 24
Peak memory 232872 kb
Host smart-d7d454a6-5e5f-4f6c-9fb2-152a25abb9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426176078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.426176078
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.313498617
Short name T871
Test name
Test status
Simulation time 50220100 ps
CPU time 0.78 seconds
Started Jun 22 06:09:55 PM PDT 24
Finished Jun 22 06:09:56 PM PDT 24
Peak memory 206752 kb
Host smart-d5750106-f5b9-447a-843f-757f1c60a327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313498617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.313498617
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1655956172
Short name T300
Test name
Test status
Simulation time 36061449560 ps
CPU time 106.84 seconds
Started Jun 22 06:10:02 PM PDT 24
Finished Jun 22 06:11:49 PM PDT 24
Peak memory 239580 kb
Host smart-ade2e832-4ce9-40ab-8c8e-379463fc1a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655956172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1655956172
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2374515116
Short name T231
Test name
Test status
Simulation time 711448923675 ps
CPU time 401.25 seconds
Started Jun 22 06:10:05 PM PDT 24
Finished Jun 22 06:16:47 PM PDT 24
Peak memory 281872 kb
Host smart-549f7422-13a3-42ef-8fa4-b357e4c70ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374515116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2374515116
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3423716508
Short name T46
Test name
Test status
Simulation time 833697166 ps
CPU time 5.93 seconds
Started Jun 22 06:10:00 PM PDT 24
Finished Jun 22 06:10:06 PM PDT 24
Peak memory 224636 kb
Host smart-d1e41627-0703-4ec5-8cbf-a669d9f553b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423716508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3423716508
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3269894018
Short name T608
Test name
Test status
Simulation time 124834326 ps
CPU time 2.71 seconds
Started Jun 22 06:10:04 PM PDT 24
Finished Jun 22 06:10:07 PM PDT 24
Peak memory 232864 kb
Host smart-51f91095-b839-41a4-a685-48435cf936b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269894018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3269894018
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.612323817
Short name T510
Test name
Test status
Simulation time 1633613443 ps
CPU time 15.37 seconds
Started Jun 22 06:10:02 PM PDT 24
Finished Jun 22 06:10:18 PM PDT 24
Peak memory 224636 kb
Host smart-0bce0027-fa12-49e7-b245-956079f0a3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612323817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.612323817
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4140401566
Short name T233
Test name
Test status
Simulation time 286031696 ps
CPU time 4.49 seconds
Started Jun 22 06:09:56 PM PDT 24
Finished Jun 22 06:10:02 PM PDT 24
Peak memory 224568 kb
Host smart-faafb9ae-27b0-4150-b511-bf3b30b0089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140401566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.4140401566
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3942081188
Short name T411
Test name
Test status
Simulation time 587372469 ps
CPU time 4.19 seconds
Started Jun 22 06:09:55 PM PDT 24
Finished Jun 22 06:10:00 PM PDT 24
Peak memory 224664 kb
Host smart-c4293028-0d48-4d99-a45c-35e55cba9e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942081188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3942081188
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.35223459
Short name T627
Test name
Test status
Simulation time 95052505 ps
CPU time 4.04 seconds
Started Jun 22 06:10:07 PM PDT 24
Finished Jun 22 06:10:12 PM PDT 24
Peak memory 223216 kb
Host smart-76211881-2f70-4ec8-a30e-9511af1f8344
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=35223459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direc
t.35223459
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2931683897
Short name T37
Test name
Test status
Simulation time 10551541534 ps
CPU time 132.4 seconds
Started Jun 22 06:10:04 PM PDT 24
Finished Jun 22 06:12:17 PM PDT 24
Peak memory 257500 kb
Host smart-48a017f8-475a-4c68-9f91-4a8f5daa8327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931683897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2931683897
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1485348219
Short name T417
Test name
Test status
Simulation time 5940572548 ps
CPU time 15.22 seconds
Started Jun 22 06:09:55 PM PDT 24
Finished Jun 22 06:10:11 PM PDT 24
Peak memory 216784 kb
Host smart-954dce8f-14ff-4191-8493-40b3d5075306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485348219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1485348219
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1213857228
Short name T520
Test name
Test status
Simulation time 1862397790 ps
CPU time 3.63 seconds
Started Jun 22 06:09:54 PM PDT 24
Finished Jun 22 06:09:58 PM PDT 24
Peak memory 216404 kb
Host smart-0765b212-0ced-46b9-8b37-ecb2a39661de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213857228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1213857228
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.880358848
Short name T670
Test name
Test status
Simulation time 51583663 ps
CPU time 1.28 seconds
Started Jun 22 06:09:56 PM PDT 24
Finished Jun 22 06:09:58 PM PDT 24
Peak memory 208260 kb
Host smart-8fb0fe98-ce5e-4182-8c3f-bb2069ad445c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880358848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.880358848
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2937945753
Short name T487
Test name
Test status
Simulation time 255704663 ps
CPU time 0.95 seconds
Started Jun 22 06:09:55 PM PDT 24
Finished Jun 22 06:09:57 PM PDT 24
Peak memory 206388 kb
Host smart-0199e4e6-2cfc-4288-bc4e-c2f34927958b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937945753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2937945753
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1141218371
Short name T767
Test name
Test status
Simulation time 3251294419 ps
CPU time 15.24 seconds
Started Jun 22 06:10:02 PM PDT 24
Finished Jun 22 06:10:18 PM PDT 24
Peak memory 232984 kb
Host smart-13a0c19f-ae39-4e86-b50a-af35f7ff03d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141218371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1141218371
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4127504950
Short name T426
Test name
Test status
Simulation time 16668984 ps
CPU time 0.71 seconds
Started Jun 22 06:10:05 PM PDT 24
Finished Jun 22 06:10:06 PM PDT 24
Peak memory 205536 kb
Host smart-761b2fe3-6849-4355-acbb-6c5d6803c4ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127504950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4127504950
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2818244023
Short name T538
Test name
Test status
Simulation time 1221644114 ps
CPU time 6.03 seconds
Started Jun 22 06:10:05 PM PDT 24
Finished Jun 22 06:10:11 PM PDT 24
Peak memory 224672 kb
Host smart-c4c69f97-0b12-444b-8a3f-2280ec29512f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818244023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2818244023
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.618794752
Short name T878
Test name
Test status
Simulation time 43979734 ps
CPU time 0.92 seconds
Started Jun 22 06:10:03 PM PDT 24
Finished Jun 22 06:10:04 PM PDT 24
Peak memory 206752 kb
Host smart-fce06491-2357-4cd2-b515-44be8ec8d1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618794752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.618794752
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.4249666853
Short name T222
Test name
Test status
Simulation time 34159532025 ps
CPU time 244.42 seconds
Started Jun 22 06:10:02 PM PDT 24
Finished Jun 22 06:14:06 PM PDT 24
Peak memory 265796 kb
Host smart-e3e5f98a-04b8-4ff1-ab0f-4744fb25da19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249666853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.4249666853
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2516503111
Short name T83
Test name
Test status
Simulation time 17661866316 ps
CPU time 188.13 seconds
Started Jun 22 06:10:03 PM PDT 24
Finished Jun 22 06:13:12 PM PDT 24
Peak memory 265832 kb
Host smart-3a062b75-6e00-494f-ad01-ab4b9e9657ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516503111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2516503111
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2685254652
Short name T63
Test name
Test status
Simulation time 10537376418 ps
CPU time 48.24 seconds
Started Jun 22 06:10:09 PM PDT 24
Finished Jun 22 06:10:58 PM PDT 24
Peak memory 231220 kb
Host smart-b8cc9c6e-8b2b-4525-b8c2-20db9c82edfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685254652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2685254652
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3687474217
Short name T3
Test name
Test status
Simulation time 497083463 ps
CPU time 2.85 seconds
Started Jun 22 06:10:09 PM PDT 24
Finished Jun 22 06:10:13 PM PDT 24
Peak memory 227572 kb
Host smart-f83ab9e5-c731-431f-b373-8c9bfb49ed36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687474217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3687474217
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1269229892
Short name T789
Test name
Test status
Simulation time 12189604742 ps
CPU time 32.53 seconds
Started Jun 22 06:10:03 PM PDT 24
Finished Jun 22 06:10:36 PM PDT 24
Peak memory 233012 kb
Host smart-4a8770cc-502f-4f54-b195-6f542dd934c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269229892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1269229892
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2243984281
Short name T683
Test name
Test status
Simulation time 3258380737 ps
CPU time 12.58 seconds
Started Jun 22 06:10:05 PM PDT 24
Finished Jun 22 06:10:18 PM PDT 24
Peak memory 240888 kb
Host smart-4fe02f09-9396-4e62-91f3-2a5a68f43f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243984281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2243984281
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3878260198
Short name T211
Test name
Test status
Simulation time 2147155783 ps
CPU time 6.17 seconds
Started Jun 22 06:10:07 PM PDT 24
Finished Jun 22 06:10:14 PM PDT 24
Peak memory 232828 kb
Host smart-c3e9c177-40ef-4905-88fd-14cac3690dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878260198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3878260198
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.616399051
Short name T421
Test name
Test status
Simulation time 44558531 ps
CPU time 0.97 seconds
Started Jun 22 06:10:08 PM PDT 24
Finished Jun 22 06:10:09 PM PDT 24
Peak memory 206916 kb
Host smart-cf39155b-09f4-4c92-8913-e950658a551c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616399051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.616399051
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.442802895
Short name T320
Test name
Test status
Simulation time 1134615504 ps
CPU time 10.73 seconds
Started Jun 22 06:10:06 PM PDT 24
Finished Jun 22 06:10:17 PM PDT 24
Peak memory 216388 kb
Host smart-138a2160-d037-480e-8cd3-5eef8d03c604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442802895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.442802895
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2748191437
Short name T866
Test name
Test status
Simulation time 27535240211 ps
CPU time 9.41 seconds
Started Jun 22 06:10:05 PM PDT 24
Finished Jun 22 06:10:15 PM PDT 24
Peak memory 216520 kb
Host smart-814d1acb-726a-49ce-aa38-e5ea8db27db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748191437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2748191437
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3492312370
Short name T332
Test name
Test status
Simulation time 207568653 ps
CPU time 1.23 seconds
Started Jun 22 06:10:07 PM PDT 24
Finished Jun 22 06:10:09 PM PDT 24
Peak memory 208068 kb
Host smart-97ec8bf8-1f46-4e57-a4da-6ff4cc42fb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492312370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3492312370
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1907992449
Short name T768
Test name
Test status
Simulation time 39844424 ps
CPU time 0.87 seconds
Started Jun 22 06:10:03 PM PDT 24
Finished Jun 22 06:10:04 PM PDT 24
Peak memory 206100 kb
Host smart-b9a868cf-db34-478a-ba0a-390e828e1f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907992449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1907992449
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2791418658
Short name T105
Test name
Test status
Simulation time 989298889 ps
CPU time 2.89 seconds
Started Jun 22 06:10:04 PM PDT 24
Finished Jun 22 06:10:07 PM PDT 24
Peak memory 224692 kb
Host smart-47546709-8732-49fb-aa3a-ed6449b0eeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791418658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2791418658
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.611069903
Short name T688
Test name
Test status
Simulation time 150045709 ps
CPU time 0.68 seconds
Started Jun 22 06:10:08 PM PDT 24
Finished Jun 22 06:10:10 PM PDT 24
Peak memory 204820 kb
Host smart-ed50e4d5-1ae9-4a7e-a09c-5453f5821a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611069903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.611069903
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1923753813
Short name T57
Test name
Test status
Simulation time 17975590217 ps
CPU time 13.42 seconds
Started Jun 22 06:10:08 PM PDT 24
Finished Jun 22 06:10:23 PM PDT 24
Peak memory 224796 kb
Host smart-7ce83e9f-c9a8-4159-9d9c-fe8f5d33b2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923753813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1923753813
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.685384586
Short name T578
Test name
Test status
Simulation time 122991052 ps
CPU time 0.8 seconds
Started Jun 22 06:10:07 PM PDT 24
Finished Jun 22 06:10:09 PM PDT 24
Peak memory 206724 kb
Host smart-43577d5b-35d3-429f-b2b4-29ecc65338ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685384586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.685384586
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.4122817452
Short name T506
Test name
Test status
Simulation time 37021568042 ps
CPU time 86.32 seconds
Started Jun 22 06:10:10 PM PDT 24
Finished Jun 22 06:11:37 PM PDT 24
Peak memory 249444 kb
Host smart-be1e019e-f4e4-4265-8763-c1478ec7d32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122817452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4122817452
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2704308004
Short name T290
Test name
Test status
Simulation time 61962141420 ps
CPU time 476.69 seconds
Started Jun 22 06:10:09 PM PDT 24
Finished Jun 22 06:18:07 PM PDT 24
Peak memory 267828 kb
Host smart-f38ac316-a5e2-4bcd-be8d-09760fe15169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704308004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2704308004
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2426701028
Short name T338
Test name
Test status
Simulation time 268874549 ps
CPU time 2.88 seconds
Started Jun 22 06:10:08 PM PDT 24
Finished Jun 22 06:10:12 PM PDT 24
Peak memory 224608 kb
Host smart-c6e83e9e-c970-45e6-8b89-2915a0978137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426701028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2426701028
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2070515249
Short name T653
Test name
Test status
Simulation time 91654418 ps
CPU time 2.19 seconds
Started Jun 22 06:10:08 PM PDT 24
Finished Jun 22 06:10:12 PM PDT 24
Peak memory 223972 kb
Host smart-7431b68e-3a06-4cb5-a906-615f7b742a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070515249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2070515249
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2581521218
Short name T195
Test name
Test status
Simulation time 12715940627 ps
CPU time 62.13 seconds
Started Jun 22 06:10:11 PM PDT 24
Finished Jun 22 06:11:13 PM PDT 24
Peak memory 232996 kb
Host smart-f1d33de7-eeaf-4562-ab44-485ab2ca0b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581521218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2581521218
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2328307783
Short name T250
Test name
Test status
Simulation time 628845116 ps
CPU time 6.63 seconds
Started Jun 22 06:10:09 PM PDT 24
Finished Jun 22 06:10:16 PM PDT 24
Peak memory 224704 kb
Host smart-4ef19a1a-4c0f-41ea-8dee-d42d48ceea27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328307783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2328307783
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3159806084
Short name T519
Test name
Test status
Simulation time 212807462 ps
CPU time 4.82 seconds
Started Jun 22 06:10:12 PM PDT 24
Finished Jun 22 06:10:17 PM PDT 24
Peak memory 222832 kb
Host smart-2118de3a-d14e-43ad-8a6d-5e0faaa554c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3159806084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3159806084
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3858299020
Short name T336
Test name
Test status
Simulation time 30222481432 ps
CPU time 39.85 seconds
Started Jun 22 06:10:08 PM PDT 24
Finished Jun 22 06:10:49 PM PDT 24
Peak memory 216548 kb
Host smart-fa3ccf60-abb6-48d2-86a4-f7ccf7cb8a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858299020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3858299020
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3285866775
Short name T953
Test name
Test status
Simulation time 5982507972 ps
CPU time 4.74 seconds
Started Jun 22 06:10:08 PM PDT 24
Finished Jun 22 06:10:14 PM PDT 24
Peak memory 216512 kb
Host smart-1a7ea929-8f6d-4d46-885f-6d21f6b7ecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285866775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3285866775
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2643416083
Short name T64
Test name
Test status
Simulation time 317296880 ps
CPU time 4.3 seconds
Started Jun 22 06:10:10 PM PDT 24
Finished Jun 22 06:10:15 PM PDT 24
Peak memory 216416 kb
Host smart-7af788b8-79f5-4bea-987f-85eb09165866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643416083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2643416083
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.594843062
Short name T360
Test name
Test status
Simulation time 70157107 ps
CPU time 0.9 seconds
Started Jun 22 06:10:08 PM PDT 24
Finished Jun 22 06:10:10 PM PDT 24
Peak memory 206096 kb
Host smart-ebe4f51e-6ea3-4ec3-994f-98f9fc5554ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594843062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.594843062
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2233309573
Short name T249
Test name
Test status
Simulation time 3519032455 ps
CPU time 13.02 seconds
Started Jun 22 06:10:09 PM PDT 24
Finished Jun 22 06:10:23 PM PDT 24
Peak memory 233016 kb
Host smart-aa258cdb-3ae2-479d-91fe-bbce63d47b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233309573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2233309573
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4080499041
Short name T664
Test name
Test status
Simulation time 1151360460 ps
CPU time 9.31 seconds
Started Jun 22 06:10:11 PM PDT 24
Finished Jun 22 06:10:21 PM PDT 24
Peak memory 224644 kb
Host smart-da8ccc59-9d11-49fc-9833-6e38fedff22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080499041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4080499041
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2078255857
Short name T669
Test name
Test status
Simulation time 53552821 ps
CPU time 0.8 seconds
Started Jun 22 06:10:07 PM PDT 24
Finished Jun 22 06:10:08 PM PDT 24
Peak memory 207068 kb
Host smart-fe1ccf58-4601-4dc0-b13e-a37644b8aa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078255857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2078255857
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1994426588
Short name T739
Test name
Test status
Simulation time 10499660187 ps
CPU time 71.65 seconds
Started Jun 22 06:10:08 PM PDT 24
Finished Jun 22 06:11:21 PM PDT 24
Peak memory 249404 kb
Host smart-e12d01b8-164b-47f3-a061-e278231cb3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994426588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1994426588
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2317355655
Short name T606
Test name
Test status
Simulation time 1071268918 ps
CPU time 15.47 seconds
Started Jun 22 06:10:09 PM PDT 24
Finished Jun 22 06:10:26 PM PDT 24
Peak memory 217696 kb
Host smart-648e0722-bde4-479f-bc16-3c19dd467c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317355655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2317355655
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3323494304
Short name T289
Test name
Test status
Simulation time 12546235558 ps
CPU time 76.75 seconds
Started Jun 22 06:10:09 PM PDT 24
Finished Jun 22 06:11:27 PM PDT 24
Peak memory 257556 kb
Host smart-9ff16ccf-927e-4a05-93d3-4da157e20692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323494304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3323494304
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3936898394
Short name T785
Test name
Test status
Simulation time 3613324440 ps
CPU time 14.66 seconds
Started Jun 22 06:10:12 PM PDT 24
Finished Jun 22 06:10:27 PM PDT 24
Peak memory 234716 kb
Host smart-c50bc27c-821c-42a2-87c3-50cc6df2cca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936898394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3936898394
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2641538023
Short name T564
Test name
Test status
Simulation time 139116283 ps
CPU time 2.92 seconds
Started Jun 22 06:10:09 PM PDT 24
Finished Jun 22 06:10:13 PM PDT 24
Peak memory 224656 kb
Host smart-29dcd4a1-a47e-4fb8-ad80-9b69130ec2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641538023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2641538023
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2610334417
Short name T839
Test name
Test status
Simulation time 10490564348 ps
CPU time 57.03 seconds
Started Jun 22 06:10:09 PM PDT 24
Finished Jun 22 06:11:07 PM PDT 24
Peak memory 249412 kb
Host smart-a8ade576-0aa4-4bb1-a712-a7792851f24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610334417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2610334417
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.403449607
Short name T468
Test name
Test status
Simulation time 381464284 ps
CPU time 5.28 seconds
Started Jun 22 06:10:08 PM PDT 24
Finished Jun 22 06:10:14 PM PDT 24
Peak memory 232868 kb
Host smart-d540d6ea-a6c5-42af-8551-d1dfc4bf7ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403449607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.403449607
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1320664804
Short name T272
Test name
Test status
Simulation time 7840489717 ps
CPU time 13.89 seconds
Started Jun 22 06:10:10 PM PDT 24
Finished Jun 22 06:10:25 PM PDT 24
Peak memory 233944 kb
Host smart-ae22f041-40fe-4e87-8516-9bf339a6bd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320664804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1320664804
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.4088065172
Short name T713
Test name
Test status
Simulation time 50995341172 ps
CPU time 102.37 seconds
Started Jun 22 06:10:08 PM PDT 24
Finished Jun 22 06:11:51 PM PDT 24
Peak memory 237008 kb
Host smart-f671b24e-b938-42cf-bfce-97d2b5a260f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088065172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.4088065172
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.644773256
Short name T327
Test name
Test status
Simulation time 2423105625 ps
CPU time 22.74 seconds
Started Jun 22 06:10:06 PM PDT 24
Finished Jun 22 06:10:29 PM PDT 24
Peak memory 216612 kb
Host smart-2296883a-e5b6-4c74-bab3-53ef61077a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644773256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.644773256
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.279596328
Short name T452
Test name
Test status
Simulation time 900307518 ps
CPU time 3.44 seconds
Started Jun 22 06:10:08 PM PDT 24
Finished Jun 22 06:10:12 PM PDT 24
Peak memory 216224 kb
Host smart-6b64e2ca-8899-486b-aa5f-8875c2b9d888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279596328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.279596328
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2151244744
Short name T450
Test name
Test status
Simulation time 18100106 ps
CPU time 0.84 seconds
Started Jun 22 06:10:11 PM PDT 24
Finished Jun 22 06:10:12 PM PDT 24
Peak memory 206104 kb
Host smart-86b2b381-0364-46a7-8162-baaf16647518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151244744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2151244744
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3846364318
Short name T629
Test name
Test status
Simulation time 123599254 ps
CPU time 0.82 seconds
Started Jun 22 06:10:07 PM PDT 24
Finished Jun 22 06:10:08 PM PDT 24
Peak memory 206096 kb
Host smart-eceed7f4-85a5-4470-8b44-c8f5a39952ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846364318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3846364318
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1708885852
Short name T409
Test name
Test status
Simulation time 588982263 ps
CPU time 4.83 seconds
Started Jun 22 06:10:10 PM PDT 24
Finished Jun 22 06:10:16 PM PDT 24
Peak memory 224700 kb
Host smart-a61d3bab-b15e-421d-8bb0-36c9c4ae8d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708885852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1708885852
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1367294168
Short name T74
Test name
Test status
Simulation time 16707264 ps
CPU time 0.71 seconds
Started Jun 22 06:10:19 PM PDT 24
Finished Jun 22 06:10:20 PM PDT 24
Peak memory 205480 kb
Host smart-98df62c9-7ac9-48e2-9471-6500add34dee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367294168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1367294168
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.4217519776
Short name T247
Test name
Test status
Simulation time 1598779454 ps
CPU time 11.68 seconds
Started Jun 22 06:10:18 PM PDT 24
Finished Jun 22 06:10:30 PM PDT 24
Peak memory 232856 kb
Host smart-c0eb89d7-5240-4607-b11d-3324b32df510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217519776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4217519776
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3117817790
Short name T568
Test name
Test status
Simulation time 25004269 ps
CPU time 0.82 seconds
Started Jun 22 06:10:19 PM PDT 24
Finished Jun 22 06:10:21 PM PDT 24
Peak memory 206684 kb
Host smart-52e887b7-d2b8-4026-8bd9-d328d4e277d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117817790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3117817790
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3669083587
Short name T706
Test name
Test status
Simulation time 97640943738 ps
CPU time 163.2 seconds
Started Jun 22 06:10:18 PM PDT 24
Finished Jun 22 06:13:02 PM PDT 24
Peak memory 249400 kb
Host smart-4a2b0c51-c4a8-4b93-bc6d-4e9b5ab53d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669083587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3669083587
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4158698986
Short name T60
Test name
Test status
Simulation time 2035918610 ps
CPU time 32.47 seconds
Started Jun 22 06:10:17 PM PDT 24
Finished Jun 22 06:10:50 PM PDT 24
Peak memory 235968 kb
Host smart-b0015128-79fe-44e2-bb6c-6f1072b2b571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158698986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4158698986
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2031789501
Short name T867
Test name
Test status
Simulation time 18045315263 ps
CPU time 130.83 seconds
Started Jun 22 06:10:19 PM PDT 24
Finished Jun 22 06:12:31 PM PDT 24
Peak memory 274208 kb
Host smart-b8834a23-5afa-4f80-99c4-d307a6c1f3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031789501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2031789501
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.743587810
Short name T838
Test name
Test status
Simulation time 1628009942 ps
CPU time 26.48 seconds
Started Jun 22 06:10:18 PM PDT 24
Finished Jun 22 06:10:45 PM PDT 24
Peak memory 241072 kb
Host smart-598418c4-1884-4cb9-9018-64d6c4a4ce55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743587810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.743587810
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2893042083
Short name T747
Test name
Test status
Simulation time 1196731043 ps
CPU time 5.38 seconds
Started Jun 22 06:10:17 PM PDT 24
Finished Jun 22 06:10:23 PM PDT 24
Peak memory 232880 kb
Host smart-6277086e-06a3-4dd1-b9e1-3f2fd4a3270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893042083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2893042083
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.220431720
Short name T831
Test name
Test status
Simulation time 12414188957 ps
CPU time 37.02 seconds
Started Jun 22 06:10:17 PM PDT 24
Finished Jun 22 06:10:54 PM PDT 24
Peak memory 233156 kb
Host smart-d8ffaf31-7668-457b-bf25-a81b23c51e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220431720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.220431720
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.807105278
Short name T266
Test name
Test status
Simulation time 382119903 ps
CPU time 5.23 seconds
Started Jun 22 06:10:17 PM PDT 24
Finished Jun 22 06:10:23 PM PDT 24
Peak memory 232816 kb
Host smart-dda4fc16-9446-4d7f-b909-0e5c35271ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807105278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.807105278
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3593293506
Short name T806
Test name
Test status
Simulation time 50347992240 ps
CPU time 19.81 seconds
Started Jun 22 06:10:18 PM PDT 24
Finished Jun 22 06:10:38 PM PDT 24
Peak memory 224768 kb
Host smart-af55049a-cd77-4836-a329-86156c7b671e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593293506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3593293506
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3974374865
Short name T943
Test name
Test status
Simulation time 1753484486 ps
CPU time 12.39 seconds
Started Jun 22 06:10:19 PM PDT 24
Finished Jun 22 06:10:32 PM PDT 24
Peak memory 219604 kb
Host smart-2c103e07-aa0d-4306-85de-d677e53c596d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3974374865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3974374865
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2660680647
Short name T774
Test name
Test status
Simulation time 17100775630 ps
CPU time 91.78 seconds
Started Jun 22 06:10:17 PM PDT 24
Finished Jun 22 06:11:49 PM PDT 24
Peak memory 257652 kb
Host smart-c859ba56-4afa-4731-9276-1d0b30b841a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660680647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2660680647
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1869836259
Short name T434
Test name
Test status
Simulation time 4291374312 ps
CPU time 12.95 seconds
Started Jun 22 06:10:19 PM PDT 24
Finished Jun 22 06:10:33 PM PDT 24
Peak memory 216536 kb
Host smart-cb0e7418-5ffc-4d8a-94a7-4674287b9a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869836259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1869836259
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3112996190
Short name T634
Test name
Test status
Simulation time 2939610258 ps
CPU time 6.13 seconds
Started Jun 22 06:10:16 PM PDT 24
Finished Jun 22 06:10:23 PM PDT 24
Peak memory 216496 kb
Host smart-81895ac5-2f9d-4f05-9b9b-44d161a106c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112996190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3112996190
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3122518385
Short name T788
Test name
Test status
Simulation time 62884516 ps
CPU time 0.85 seconds
Started Jun 22 06:10:17 PM PDT 24
Finished Jun 22 06:10:19 PM PDT 24
Peak memory 206776 kb
Host smart-a9eca0de-f444-4f25-8463-dc7ccb2c412f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122518385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3122518385
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1288548259
Short name T560
Test name
Test status
Simulation time 78508104 ps
CPU time 0.74 seconds
Started Jun 22 06:10:19 PM PDT 24
Finished Jun 22 06:10:20 PM PDT 24
Peak memory 206040 kb
Host smart-864777b2-edb1-4310-bea9-2463c48deb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288548259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1288548259
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1323363009
Short name T433
Test name
Test status
Simulation time 90908274 ps
CPU time 2.34 seconds
Started Jun 22 06:10:15 PM PDT 24
Finished Jun 22 06:10:18 PM PDT 24
Peak memory 224628 kb
Host smart-f081b80b-e8b3-4ccf-b46a-5831e2a27670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323363009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1323363009
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3580743498
Short name T703
Test name
Test status
Simulation time 13726689 ps
CPU time 0.73 seconds
Started Jun 22 06:10:23 PM PDT 24
Finished Jun 22 06:10:24 PM PDT 24
Peak memory 205528 kb
Host smart-f1e7408b-8863-41ed-b8ba-4b7f876d96b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580743498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3580743498
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4037196030
Short name T502
Test name
Test status
Simulation time 2475284436 ps
CPU time 22.63 seconds
Started Jun 22 06:10:18 PM PDT 24
Finished Jun 22 06:10:42 PM PDT 24
Peak memory 233000 kb
Host smart-108e8ed4-5e02-4953-877b-eeb5f3021a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037196030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4037196030
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2861013944
Short name T72
Test name
Test status
Simulation time 26104363 ps
CPU time 0.75 seconds
Started Jun 22 06:10:18 PM PDT 24
Finished Jun 22 06:10:19 PM PDT 24
Peak memory 205680 kb
Host smart-782f4be3-2bc1-4201-97aa-1bef23fc0d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861013944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2861013944
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.613267658
Short name T196
Test name
Test status
Simulation time 73549319744 ps
CPU time 137.86 seconds
Started Jun 22 06:10:28 PM PDT 24
Finished Jun 22 06:12:47 PM PDT 24
Peak memory 249392 kb
Host smart-d3b7cc60-990d-403b-88b5-a697f7ca809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613267658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.613267658
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.695488287
Short name T54
Test name
Test status
Simulation time 3217624143 ps
CPU time 45.41 seconds
Started Jun 22 06:10:23 PM PDT 24
Finished Jun 22 06:11:09 PM PDT 24
Peak memory 249444 kb
Host smart-beb073f7-497c-48ea-86b6-fa714986683d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695488287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.695488287
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3234030488
Short name T919
Test name
Test status
Simulation time 5868482087 ps
CPU time 26.53 seconds
Started Jun 22 06:10:27 PM PDT 24
Finished Jun 22 06:10:54 PM PDT 24
Peak memory 224736 kb
Host smart-5065b997-84ae-438e-86b3-df33ecbd8729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234030488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3234030488
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3068956215
Short name T686
Test name
Test status
Simulation time 516601357 ps
CPU time 5.48 seconds
Started Jun 22 06:10:17 PM PDT 24
Finished Jun 22 06:10:23 PM PDT 24
Peak memory 232840 kb
Host smart-2d782865-64da-45b8-9716-19359ff2ad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068956215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3068956215
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.499261463
Short name T680
Test name
Test status
Simulation time 3834799146 ps
CPU time 6.59 seconds
Started Jun 22 06:10:16 PM PDT 24
Finished Jun 22 06:10:23 PM PDT 24
Peak memory 233000 kb
Host smart-654813b8-6e88-4dff-8418-74926e033a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499261463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.499261463
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3380664836
Short name T420
Test name
Test status
Simulation time 2863436510 ps
CPU time 38.81 seconds
Started Jun 22 06:10:18 PM PDT 24
Finished Jun 22 06:10:58 PM PDT 24
Peak memory 232972 kb
Host smart-d97bca2d-f182-4b37-85ec-4fd737399575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380664836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3380664836
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3637750543
Short name T268
Test name
Test status
Simulation time 7147129910 ps
CPU time 6.56 seconds
Started Jun 22 06:10:15 PM PDT 24
Finished Jun 22 06:10:22 PM PDT 24
Peak memory 232908 kb
Host smart-7ef3009d-31d5-4cb8-a9ae-203906389920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637750543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3637750543
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.204188369
Short name T702
Test name
Test status
Simulation time 11427825121 ps
CPU time 31.04 seconds
Started Jun 22 06:10:19 PM PDT 24
Finished Jun 22 06:10:51 PM PDT 24
Peak memory 240556 kb
Host smart-512fe46c-6787-4b0f-8b7d-623bf1c1a367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204188369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.204188369
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1348235090
Short name T403
Test name
Test status
Simulation time 486306497 ps
CPU time 6.07 seconds
Started Jun 22 06:10:23 PM PDT 24
Finished Jun 22 06:10:29 PM PDT 24
Peak memory 223316 kb
Host smart-75725d0a-aba4-4cc4-a3d5-95c856087fb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1348235090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1348235090
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.108336461
Short name T292
Test name
Test status
Simulation time 175421441248 ps
CPU time 464.37 seconds
Started Jun 22 06:10:29 PM PDT 24
Finished Jun 22 06:18:14 PM PDT 24
Peak memory 251388 kb
Host smart-776b8024-ec16-4256-ad2b-30e78327274a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108336461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.108336461
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.738186331
Short name T945
Test name
Test status
Simulation time 7680634114 ps
CPU time 13.64 seconds
Started Jun 22 06:10:18 PM PDT 24
Finished Jun 22 06:10:32 PM PDT 24
Peak memory 216572 kb
Host smart-b3eb916d-e67b-4efc-bf00-7c556f0fd025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738186331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.738186331
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2511146190
Short name T535
Test name
Test status
Simulation time 4930636334 ps
CPU time 3.48 seconds
Started Jun 22 06:10:17 PM PDT 24
Finished Jun 22 06:10:21 PM PDT 24
Peak memory 216532 kb
Host smart-c46fee60-e785-4172-817d-38fa5e5824ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511146190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2511146190
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3775056388
Short name T558
Test name
Test status
Simulation time 71404080 ps
CPU time 0.89 seconds
Started Jun 22 06:10:17 PM PDT 24
Finished Jun 22 06:10:18 PM PDT 24
Peak memory 206248 kb
Host smart-31aed627-8fd0-4450-ae1c-48d959f75f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775056388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3775056388
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3795578807
Short name T430
Test name
Test status
Simulation time 264982568 ps
CPU time 1.02 seconds
Started Jun 22 06:10:20 PM PDT 24
Finished Jun 22 06:10:21 PM PDT 24
Peak memory 206508 kb
Host smart-4a463066-c913-432b-b5e0-3963672ddf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795578807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3795578807
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1573839942
Short name T526
Test name
Test status
Simulation time 108952522 ps
CPU time 2.93 seconds
Started Jun 22 06:10:17 PM PDT 24
Finished Jun 22 06:10:21 PM PDT 24
Peak memory 232808 kb
Host smart-2c3f79e2-f471-47d4-abf3-6db6393567d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573839942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1573839942
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.579741663
Short name T576
Test name
Test status
Simulation time 12702045 ps
CPU time 0.72 seconds
Started Jun 22 06:10:25 PM PDT 24
Finished Jun 22 06:10:26 PM PDT 24
Peak memory 205536 kb
Host smart-bc9871e1-0880-45ec-a57b-5ae3c077f4f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579741663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.579741663
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2640569304
Short name T416
Test name
Test status
Simulation time 47489955 ps
CPU time 2.63 seconds
Started Jun 22 06:10:22 PM PDT 24
Finished Jun 22 06:10:25 PM PDT 24
Peak memory 224636 kb
Host smart-1e2f250e-b863-451a-be7d-1d55327bdb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640569304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2640569304
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3590779082
Short name T395
Test name
Test status
Simulation time 16630185 ps
CPU time 0.79 seconds
Started Jun 22 06:10:22 PM PDT 24
Finished Jun 22 06:10:24 PM PDT 24
Peak memory 206728 kb
Host smart-9c4e639a-0c93-4ede-afef-e8473cfda918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590779082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3590779082
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3141610436
Short name T279
Test name
Test status
Simulation time 1145638690 ps
CPU time 20.3 seconds
Started Jun 22 06:10:24 PM PDT 24
Finished Jun 22 06:10:45 PM PDT 24
Peak memory 224728 kb
Host smart-5e6fd1f2-a8e1-4056-bf90-75a8d3fe61c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141610436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3141610436
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4155159613
Short name T612
Test name
Test status
Simulation time 657145236 ps
CPU time 13.06 seconds
Started Jun 22 06:10:27 PM PDT 24
Finished Jun 22 06:10:40 PM PDT 24
Peak memory 232896 kb
Host smart-76cfc22c-7dfb-40ce-b4d3-51abcb46039f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155159613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4155159613
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1048305758
Short name T584
Test name
Test status
Simulation time 522690784 ps
CPU time 6.96 seconds
Started Jun 22 06:10:27 PM PDT 24
Finished Jun 22 06:10:35 PM PDT 24
Peak memory 224616 kb
Host smart-e15d473a-a2f6-4d57-92ab-b1ace69618d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048305758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1048305758
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3219821631
Short name T574
Test name
Test status
Simulation time 970690526 ps
CPU time 15.53 seconds
Started Jun 22 06:10:27 PM PDT 24
Finished Jun 22 06:10:43 PM PDT 24
Peak memory 224452 kb
Host smart-67d52199-c80b-4357-9ed9-97aa1ea9d0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219821631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3219821631
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3760163489
Short name T269
Test name
Test status
Simulation time 53739146420 ps
CPU time 37.4 seconds
Started Jun 22 06:10:32 PM PDT 24
Finished Jun 22 06:11:10 PM PDT 24
Peak memory 232880 kb
Host smart-7c33fea0-4d0f-4fce-97cd-eea0fc56c79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760163489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3760163489
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2455170150
Short name T214
Test name
Test status
Simulation time 1575422989 ps
CPU time 5.88 seconds
Started Jun 22 06:10:24 PM PDT 24
Finished Jun 22 06:10:30 PM PDT 24
Peak memory 240680 kb
Host smart-e41c740a-0a74-4135-bf70-2c2ec38bf740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455170150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2455170150
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3797764940
Short name T155
Test name
Test status
Simulation time 302696919 ps
CPU time 4.35 seconds
Started Jun 22 06:10:27 PM PDT 24
Finished Jun 22 06:10:32 PM PDT 24
Peak memory 223128 kb
Host smart-2b64e3cf-fb87-425a-9157-b26d6a70b3d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3797764940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3797764940
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2352519246
Short name T255
Test name
Test status
Simulation time 59756580293 ps
CPU time 537.22 seconds
Started Jun 22 06:10:28 PM PDT 24
Finished Jun 22 06:19:26 PM PDT 24
Peak memory 267624 kb
Host smart-6b6e58eb-b50a-42f9-9e6d-0b250fc6b571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352519246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2352519246
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2846578389
Short name T641
Test name
Test status
Simulation time 35064035252 ps
CPU time 44.82 seconds
Started Jun 22 06:10:30 PM PDT 24
Finished Jun 22 06:11:16 PM PDT 24
Peak memory 216484 kb
Host smart-6648cc7c-615b-4c27-bda6-920e4c0fc3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846578389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2846578389
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3438760687
Short name T770
Test name
Test status
Simulation time 906295150 ps
CPU time 5.37 seconds
Started Jun 22 06:10:27 PM PDT 24
Finished Jun 22 06:10:33 PM PDT 24
Peak memory 216440 kb
Host smart-827c9940-8ea7-4c68-89a7-82ea623bb691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438760687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3438760687
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.14701801
Short name T835
Test name
Test status
Simulation time 11912205 ps
CPU time 0.71 seconds
Started Jun 22 06:10:27 PM PDT 24
Finished Jun 22 06:10:28 PM PDT 24
Peak memory 205720 kb
Host smart-35074ebe-bab0-40df-bae3-6cac8ca7bf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14701801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.14701801
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3442091290
Short name T756
Test name
Test status
Simulation time 22127712 ps
CPU time 0.75 seconds
Started Jun 22 06:10:23 PM PDT 24
Finished Jun 22 06:10:25 PM PDT 24
Peak memory 205672 kb
Host smart-2d6f1168-2056-4616-8db1-825b6c48c577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442091290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3442091290
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2756065822
Short name T848
Test name
Test status
Simulation time 13150270959 ps
CPU time 19.13 seconds
Started Jun 22 06:10:25 PM PDT 24
Finished Jun 22 06:10:45 PM PDT 24
Peak memory 233004 kb
Host smart-f4126841-1c68-4145-af7c-71bc424dcb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756065822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2756065822
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1148015013
Short name T24
Test name
Test status
Simulation time 44167135 ps
CPU time 0.73 seconds
Started Jun 22 06:10:25 PM PDT 24
Finished Jun 22 06:10:26 PM PDT 24
Peak memory 205416 kb
Host smart-afe4e4a3-1237-4b2e-b7fb-7c672771fba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148015013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1148015013
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4039250202
Short name T698
Test name
Test status
Simulation time 1265589425 ps
CPU time 4.99 seconds
Started Jun 22 06:10:24 PM PDT 24
Finished Jun 22 06:10:29 PM PDT 24
Peak memory 224596 kb
Host smart-8db9116a-331f-4508-8383-abb5d9abec7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039250202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4039250202
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3378798383
Short name T459
Test name
Test status
Simulation time 15383776 ps
CPU time 0.77 seconds
Started Jun 22 06:10:23 PM PDT 24
Finished Jun 22 06:10:24 PM PDT 24
Peak memory 205720 kb
Host smart-577c4643-2c84-4cac-8137-75e58f7fe266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378798383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3378798383
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2871390610
Short name T206
Test name
Test status
Simulation time 103321247585 ps
CPU time 96.15 seconds
Started Jun 22 06:10:29 PM PDT 24
Finished Jun 22 06:12:06 PM PDT 24
Peak memory 251416 kb
Host smart-ee90d790-0462-4dfe-aa9c-3d5a2d4d89d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871390610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2871390610
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.4118535339
Short name T792
Test name
Test status
Simulation time 5550219101 ps
CPU time 81.07 seconds
Started Jun 22 06:10:25 PM PDT 24
Finished Jun 22 06:11:46 PM PDT 24
Peak memory 252464 kb
Host smart-058a0a00-5d13-4c2b-917a-cc63982f9eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118535339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.4118535339
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1419479408
Short name T317
Test name
Test status
Simulation time 480247814 ps
CPU time 5.3 seconds
Started Jun 22 06:10:23 PM PDT 24
Finished Jun 22 06:10:30 PM PDT 24
Peak memory 233936 kb
Host smart-a5734966-1de4-408d-80a1-b25b9df102cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419479408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1419479408
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3162393124
Short name T521
Test name
Test status
Simulation time 73111331 ps
CPU time 2.26 seconds
Started Jun 22 06:10:28 PM PDT 24
Finished Jun 22 06:10:31 PM PDT 24
Peak memory 222972 kb
Host smart-72c73b91-4c81-4744-98ec-97ac677d951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162393124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3162393124
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3146421120
Short name T622
Test name
Test status
Simulation time 117197065 ps
CPU time 2.43 seconds
Started Jun 22 06:10:25 PM PDT 24
Finished Jun 22 06:10:28 PM PDT 24
Peak memory 232576 kb
Host smart-eab165a6-a289-4d29-ab6e-a788a9644a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146421120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3146421120
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.4070604125
Short name T740
Test name
Test status
Simulation time 326369699 ps
CPU time 5.83 seconds
Started Jun 22 06:10:23 PM PDT 24
Finished Jun 22 06:10:30 PM PDT 24
Peak memory 232844 kb
Host smart-cad9e479-b849-411b-adf6-bc1e1e59d68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070604125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.4070604125
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2144100945
Short name T497
Test name
Test status
Simulation time 3919694265 ps
CPU time 11.88 seconds
Started Jun 22 06:10:21 PM PDT 24
Finished Jun 22 06:10:33 PM PDT 24
Peak memory 224680 kb
Host smart-a0255e48-d56b-429e-971f-7955593653ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144100945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2144100945
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3900292425
Short name T480
Test name
Test status
Simulation time 4770500686 ps
CPU time 6.02 seconds
Started Jun 22 06:10:23 PM PDT 24
Finished Jun 22 06:10:30 PM PDT 24
Peak memory 219128 kb
Host smart-6e33de70-2ac9-40a1-ac48-019b823ba2ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3900292425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3900292425
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2139029029
Short name T191
Test name
Test status
Simulation time 5993019926 ps
CPU time 88.85 seconds
Started Jun 22 06:10:27 PM PDT 24
Finished Jun 22 06:11:56 PM PDT 24
Peak memory 254236 kb
Host smart-295ace8a-d64f-420d-acf0-99b6fd1c6164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139029029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2139029029
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1291488873
Short name T630
Test name
Test status
Simulation time 1752993769 ps
CPU time 14.86 seconds
Started Jun 22 06:10:28 PM PDT 24
Finished Jun 22 06:10:43 PM PDT 24
Peak memory 219392 kb
Host smart-0c2343ab-2cf2-4580-ad81-ad90e67ec8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291488873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1291488873
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1220440912
Short name T672
Test name
Test status
Simulation time 1908675743 ps
CPU time 5.8 seconds
Started Jun 22 06:10:33 PM PDT 24
Finished Jun 22 06:10:39 PM PDT 24
Peak memory 216312 kb
Host smart-1c44912b-367e-4d21-a2b8-33714d339d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220440912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1220440912
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1404053127
Short name T429
Test name
Test status
Simulation time 234466714 ps
CPU time 2.85 seconds
Started Jun 22 06:10:25 PM PDT 24
Finished Jun 22 06:10:29 PM PDT 24
Peak memory 216284 kb
Host smart-f16543c3-2a9b-447a-90de-47986ab48b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404053127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1404053127
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3091231652
Short name T851
Test name
Test status
Simulation time 38128809 ps
CPU time 0.81 seconds
Started Jun 22 06:10:23 PM PDT 24
Finished Jun 22 06:10:25 PM PDT 24
Peak memory 206096 kb
Host smart-99587dec-1e2a-4f6b-ad74-6eabb852186f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091231652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3091231652
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2050236951
Short name T235
Test name
Test status
Simulation time 14931884554 ps
CPU time 9.6 seconds
Started Jun 22 06:10:23 PM PDT 24
Finished Jun 22 06:10:34 PM PDT 24
Peak memory 233020 kb
Host smart-098691ae-9681-46a6-b289-031fa2d41bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050236951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2050236951
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3606537237
Short name T870
Test name
Test status
Simulation time 11563309 ps
CPU time 0.71 seconds
Started Jun 22 06:10:30 PM PDT 24
Finished Jun 22 06:10:32 PM PDT 24
Peak memory 204936 kb
Host smart-0c8c4c6d-98af-4467-9f90-1cf4e3b4aa2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606537237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3606537237
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2105002128
Short name T28
Test name
Test status
Simulation time 484599734 ps
CPU time 4.68 seconds
Started Jun 22 06:10:33 PM PDT 24
Finished Jun 22 06:10:38 PM PDT 24
Peak memory 232872 kb
Host smart-9b52ab4d-ab56-4f19-854a-79a90fd68367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105002128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2105002128
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1733161156
Short name T509
Test name
Test status
Simulation time 40416663 ps
CPU time 0.74 seconds
Started Jun 22 06:10:28 PM PDT 24
Finished Jun 22 06:10:30 PM PDT 24
Peak memory 205724 kb
Host smart-91473d5f-5670-4cbe-bcfa-d2b4618b7902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733161156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1733161156
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3850809985
Short name T926
Test name
Test status
Simulation time 57548017995 ps
CPU time 120.25 seconds
Started Jun 22 06:10:31 PM PDT 24
Finished Jun 22 06:12:31 PM PDT 24
Peak memory 249372 kb
Host smart-c53a6244-c6d8-47a6-9a60-2909d5880c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850809985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3850809985
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2857171631
Short name T855
Test name
Test status
Simulation time 750839500983 ps
CPU time 526.11 seconds
Started Jun 22 06:10:30 PM PDT 24
Finished Jun 22 06:19:17 PM PDT 24
Peak memory 257092 kb
Host smart-d68eee24-6288-4748-bf68-0890f30009bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857171631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2857171631
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1276297156
Short name T85
Test name
Test status
Simulation time 53918136206 ps
CPU time 175.45 seconds
Started Jun 22 06:10:33 PM PDT 24
Finished Jun 22 06:13:29 PM PDT 24
Peak memory 257640 kb
Host smart-90af439b-1644-402c-bd79-7dedd95ee3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276297156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1276297156
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.474952302
Short name T849
Test name
Test status
Simulation time 2455074498 ps
CPU time 40.86 seconds
Started Jun 22 06:10:27 PM PDT 24
Finished Jun 22 06:11:09 PM PDT 24
Peak memory 224696 kb
Host smart-6e799c21-7f47-40f5-8d1e-b429775afb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474952302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.474952302
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3765992301
Short name T637
Test name
Test status
Simulation time 129207247 ps
CPU time 2.11 seconds
Started Jun 22 06:10:31 PM PDT 24
Finished Jun 22 06:10:34 PM PDT 24
Peak memory 222864 kb
Host smart-7d9384af-c8f1-4d1e-8044-0a24dbb2f601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765992301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3765992301
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3408510658
Short name T798
Test name
Test status
Simulation time 1926097016 ps
CPU time 18.92 seconds
Started Jun 22 06:10:30 PM PDT 24
Finished Jun 22 06:10:49 PM PDT 24
Peak memory 224644 kb
Host smart-f94bd121-b59b-44cf-ab8a-296ca1825f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408510658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3408510658
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1613780536
Short name T237
Test name
Test status
Simulation time 13341352400 ps
CPU time 34.16 seconds
Started Jun 22 06:10:27 PM PDT 24
Finished Jun 22 06:11:02 PM PDT 24
Peak memory 248732 kb
Host smart-687bdc0b-5bc7-406f-b3ce-7093488ae50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613780536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1613780536
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.812834594
Short name T661
Test name
Test status
Simulation time 73482045491 ps
CPU time 15.85 seconds
Started Jun 22 06:10:27 PM PDT 24
Finished Jun 22 06:10:44 PM PDT 24
Peak memory 232988 kb
Host smart-a31ace2f-4f8d-4f00-bf1f-d0bba92f316c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812834594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.812834594
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2721423866
Short name T153
Test name
Test status
Simulation time 932770947 ps
CPU time 4.94 seconds
Started Jun 22 06:10:29 PM PDT 24
Finished Jun 22 06:10:35 PM PDT 24
Peak memory 220208 kb
Host smart-003e4e2f-529a-4659-8239-5291159efebe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2721423866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2721423866
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2149967814
Short name T660
Test name
Test status
Simulation time 38250116746 ps
CPU time 258.03 seconds
Started Jun 22 06:10:32 PM PDT 24
Finished Jun 22 06:14:50 PM PDT 24
Peak memory 256688 kb
Host smart-da97c951-a9ab-4eec-9f3a-acca9219a9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149967814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2149967814
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1369726717
Short name T892
Test name
Test status
Simulation time 2995081708 ps
CPU time 15.93 seconds
Started Jun 22 06:10:28 PM PDT 24
Finished Jun 22 06:10:45 PM PDT 24
Peak memory 216544 kb
Host smart-13597f52-6b2c-45d7-a261-3a87f3477052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369726717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1369726717
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3875821062
Short name T142
Test name
Test status
Simulation time 1028087970 ps
CPU time 5.19 seconds
Started Jun 22 06:10:27 PM PDT 24
Finished Jun 22 06:10:33 PM PDT 24
Peak memory 216368 kb
Host smart-27d52cc2-2a2e-4057-8722-0f013c2d9980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875821062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3875821062
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2686134645
Short name T823
Test name
Test status
Simulation time 29930228 ps
CPU time 1.04 seconds
Started Jun 22 06:10:32 PM PDT 24
Finished Jun 22 06:10:34 PM PDT 24
Peak memory 207292 kb
Host smart-97b10236-d945-4dd5-9768-70b95b74e7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686134645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2686134645
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4080602214
Short name T657
Test name
Test status
Simulation time 92542374 ps
CPU time 0.81 seconds
Started Jun 22 06:10:22 PM PDT 24
Finished Jun 22 06:10:24 PM PDT 24
Peak memory 206092 kb
Host smart-e096b41f-b00a-466a-8795-4143cd4fd9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080602214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4080602214
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2316872157
Short name T948
Test name
Test status
Simulation time 1047544597 ps
CPU time 4.34 seconds
Started Jun 22 06:10:30 PM PDT 24
Finished Jun 22 06:10:35 PM PDT 24
Peak memory 232892 kb
Host smart-02030ff1-4faa-4afe-a803-11ec0b965065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316872157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2316872157
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3599291315
Short name T795
Test name
Test status
Simulation time 44352368 ps
CPU time 0.75 seconds
Started Jun 22 06:10:38 PM PDT 24
Finished Jun 22 06:10:40 PM PDT 24
Peak memory 205420 kb
Host smart-12fbf208-6126-4731-8c3b-fe73518e2b37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599291315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3599291315
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2949989910
Short name T189
Test name
Test status
Simulation time 1332003549 ps
CPU time 8.44 seconds
Started Jun 22 06:10:30 PM PDT 24
Finished Jun 22 06:10:40 PM PDT 24
Peak memory 232876 kb
Host smart-25ddfcc7-2f49-45f7-98da-d8fc999f48a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949989910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2949989910
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1068947160
Short name T732
Test name
Test status
Simulation time 20630139 ps
CPU time 0.81 seconds
Started Jun 22 06:10:30 PM PDT 24
Finished Jun 22 06:10:31 PM PDT 24
Peak memory 206720 kb
Host smart-53253d0b-9ba2-4a44-945b-5a076d595e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068947160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1068947160
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3011445015
Short name T722
Test name
Test status
Simulation time 41653099993 ps
CPU time 178.25 seconds
Started Jun 22 06:10:31 PM PDT 24
Finished Jun 22 06:13:30 PM PDT 24
Peak memory 255844 kb
Host smart-32897986-41e9-4602-955f-501439c46746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011445015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3011445015
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.321741288
Short name T68
Test name
Test status
Simulation time 384067348 ps
CPU time 6.55 seconds
Started Jun 22 06:10:30 PM PDT 24
Finished Jun 22 06:10:37 PM PDT 24
Peak memory 241040 kb
Host smart-d26a69cd-0f40-476f-a8e4-db3f8e34e691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321741288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.321741288
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4020040474
Short name T172
Test name
Test status
Simulation time 1209565569 ps
CPU time 8.34 seconds
Started Jun 22 06:10:33 PM PDT 24
Finished Jun 22 06:10:42 PM PDT 24
Peak memory 218840 kb
Host smart-88913a8b-9409-482d-a291-0eda8a1258f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020040474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4020040474
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3166069405
Short name T271
Test name
Test status
Simulation time 77908305645 ps
CPU time 74.4 seconds
Started Jun 22 06:10:31 PM PDT 24
Finished Jun 22 06:11:46 PM PDT 24
Peak memory 241204 kb
Host smart-ca8b1dac-a74b-413b-a3ea-dbb1194ae8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166069405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3166069405
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3571476898
Short name T721
Test name
Test status
Simulation time 7316457977 ps
CPU time 21.21 seconds
Started Jun 22 06:10:30 PM PDT 24
Finished Jun 22 06:10:52 PM PDT 24
Peak memory 224704 kb
Host smart-bb499f14-c322-4b3a-834a-18503acb3549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571476898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3571476898
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2386910782
Short name T543
Test name
Test status
Simulation time 186192984 ps
CPU time 4.31 seconds
Started Jun 22 06:10:34 PM PDT 24
Finished Jun 22 06:10:38 PM PDT 24
Peak memory 224584 kb
Host smart-1d66e790-744f-4449-8471-89f3fded2ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386910782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2386910782
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3658696177
Short name T726
Test name
Test status
Simulation time 1834798718 ps
CPU time 7.64 seconds
Started Jun 22 06:10:33 PM PDT 24
Finished Jun 22 06:10:41 PM PDT 24
Peak memory 223312 kb
Host smart-d5deeb13-397c-4415-bc8a-f0179d9f5d3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3658696177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3658696177
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3711142215
Short name T164
Test name
Test status
Simulation time 598634285 ps
CPU time 1 seconds
Started Jun 22 06:10:31 PM PDT 24
Finished Jun 22 06:10:33 PM PDT 24
Peak memory 206856 kb
Host smart-599064e8-78cd-41d3-8d4a-c3b649645e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711142215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3711142215
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.4142818503
Short name T777
Test name
Test status
Simulation time 530193254 ps
CPU time 3.74 seconds
Started Jun 22 06:10:30 PM PDT 24
Finished Jun 22 06:10:34 PM PDT 24
Peak memory 216400 kb
Host smart-4a8d2b29-7e8c-469d-b485-4fcdf7236868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142818503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4142818503
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.223336225
Short name T493
Test name
Test status
Simulation time 1872592421 ps
CPU time 5.92 seconds
Started Jun 22 06:10:29 PM PDT 24
Finished Jun 22 06:10:36 PM PDT 24
Peak memory 216384 kb
Host smart-51251076-305d-47e4-9b8b-68dd0c3c1698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223336225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.223336225
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3737863857
Short name T955
Test name
Test status
Simulation time 120292740 ps
CPU time 2.72 seconds
Started Jun 22 06:10:30 PM PDT 24
Finished Jun 22 06:10:33 PM PDT 24
Peak memory 216388 kb
Host smart-999d94d7-21eb-4e35-abfc-47414ef3686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737863857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3737863857
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.957805208
Short name T930
Test name
Test status
Simulation time 160249204 ps
CPU time 0.82 seconds
Started Jun 22 06:10:29 PM PDT 24
Finished Jun 22 06:10:31 PM PDT 24
Peak memory 206048 kb
Host smart-d3c0bbad-4203-403f-b90d-389b6bc87c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957805208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.957805208
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1337452435
Short name T492
Test name
Test status
Simulation time 346388485 ps
CPU time 5.88 seconds
Started Jun 22 06:10:30 PM PDT 24
Finished Jun 22 06:10:37 PM PDT 24
Peak memory 240088 kb
Host smart-ce05db21-5806-464c-bcd2-0a910444a0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337452435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1337452435
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3488383178
Short name T363
Test name
Test status
Simulation time 13046987 ps
CPU time 0.7 seconds
Started Jun 22 06:09:33 PM PDT 24
Finished Jun 22 06:09:34 PM PDT 24
Peak memory 205524 kb
Host smart-e7183a4b-7cdf-4b4f-9612-4a55b90dafff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488383178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
488383178
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.231618676
Short name T256
Test name
Test status
Simulation time 35027791 ps
CPU time 2.43 seconds
Started Jun 22 06:09:28 PM PDT 24
Finished Jun 22 06:09:32 PM PDT 24
Peak memory 232892 kb
Host smart-d1dbbbaa-ce3b-4d1a-a2d2-4fd34f41cd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231618676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.231618676
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2560868167
Short name T694
Test name
Test status
Simulation time 13137422 ps
CPU time 0.75 seconds
Started Jun 22 06:09:29 PM PDT 24
Finished Jun 22 06:09:31 PM PDT 24
Peak memory 205724 kb
Host smart-b8286b1c-8f91-44d3-a2e6-a9156ec17965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560868167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2560868167
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.886980937
Short name T357
Test name
Test status
Simulation time 9654382597 ps
CPU time 35.05 seconds
Started Jun 22 06:09:29 PM PDT 24
Finished Jun 22 06:10:05 PM PDT 24
Peak memory 238384 kb
Host smart-9c07b104-4bb9-4ab6-ac37-757e8c058659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886980937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.886980937
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.581717529
Short name T207
Test name
Test status
Simulation time 4252251230 ps
CPU time 101.97 seconds
Started Jun 22 06:09:27 PM PDT 24
Finished Jun 22 06:11:10 PM PDT 24
Peak memory 255232 kb
Host smart-67485da3-d92b-490f-8cba-3b72c93bcacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581717529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.581717529
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1495729064
Short name T307
Test name
Test status
Simulation time 24690572392 ps
CPU time 114.55 seconds
Started Jun 22 06:09:28 PM PDT 24
Finished Jun 22 06:11:23 PM PDT 24
Peak memory 254392 kb
Host smart-6ff8b3ee-b08a-45c2-9496-494aeeba613e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495729064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1495729064
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4078610026
Short name T9
Test name
Test status
Simulation time 1482097170 ps
CPU time 19.58 seconds
Started Jun 22 06:09:29 PM PDT 24
Finished Jun 22 06:09:49 PM PDT 24
Peak memory 234104 kb
Host smart-e179b74c-2aae-405b-8db6-24fd0af51c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078610026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4078610026
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3907486544
Short name T700
Test name
Test status
Simulation time 1362655462 ps
CPU time 3.85 seconds
Started Jun 22 06:09:29 PM PDT 24
Finished Jun 22 06:09:34 PM PDT 24
Peak memory 224568 kb
Host smart-e6ebd643-2f8a-4176-9d8a-2e7a976948dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907486544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3907486544
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.833364900
Short name T717
Test name
Test status
Simulation time 982968546 ps
CPU time 9.38 seconds
Started Jun 22 06:09:32 PM PDT 24
Finished Jun 22 06:09:42 PM PDT 24
Peak memory 232572 kb
Host smart-bdf53056-829e-483a-9733-2ded8c578970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833364900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.833364900
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2623666912
Short name T441
Test name
Test status
Simulation time 1348944938 ps
CPU time 5.95 seconds
Started Jun 22 06:09:28 PM PDT 24
Finished Jun 22 06:09:35 PM PDT 24
Peak memory 240844 kb
Host smart-129650ed-8e55-4cf7-bcfa-43611f480f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623666912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2623666912
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3953421244
Short name T542
Test name
Test status
Simulation time 23712012286 ps
CPU time 12.95 seconds
Started Jun 22 06:09:27 PM PDT 24
Finished Jun 22 06:09:40 PM PDT 24
Peak memory 224764 kb
Host smart-83c4d750-528d-433b-8801-5d7c58cff0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953421244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3953421244
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3103333460
Short name T776
Test name
Test status
Simulation time 945922843 ps
CPU time 9.52 seconds
Started Jun 22 06:09:32 PM PDT 24
Finished Jun 22 06:09:42 PM PDT 24
Peak memory 223336 kb
Host smart-631b2104-90d0-4283-9dfa-8c2d004ca4ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3103333460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3103333460
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3228799160
Short name T80
Test name
Test status
Simulation time 32254397 ps
CPU time 0.98 seconds
Started Jun 22 06:09:28 PM PDT 24
Finished Jun 22 06:09:29 PM PDT 24
Peak memory 235820 kb
Host smart-845e5d20-8a45-48d9-b06d-91c8ecd74eba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228799160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3228799160
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3793585622
Short name T862
Test name
Test status
Simulation time 68566091 ps
CPU time 1.25 seconds
Started Jun 22 06:09:30 PM PDT 24
Finished Jun 22 06:09:31 PM PDT 24
Peak memory 206916 kb
Host smart-8fd8aeb2-bce5-4513-9beb-f2e1a382bc4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793585622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3793585622
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2631762783
Short name T419
Test name
Test status
Simulation time 4119924010 ps
CPU time 28.33 seconds
Started Jun 22 06:09:28 PM PDT 24
Finished Jun 22 06:09:57 PM PDT 24
Peak memory 216528 kb
Host smart-d656b725-b239-4466-8589-f16a80e4a1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631762783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2631762783
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2344653453
Short name T501
Test name
Test status
Simulation time 878926396 ps
CPU time 5.5 seconds
Started Jun 22 06:09:32 PM PDT 24
Finished Jun 22 06:09:38 PM PDT 24
Peak memory 216220 kb
Host smart-03fcbe63-7067-49ea-b16a-e02f3cc42d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344653453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2344653453
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2303856688
Short name T718
Test name
Test status
Simulation time 17457567 ps
CPU time 0.76 seconds
Started Jun 22 06:09:28 PM PDT 24
Finished Jun 22 06:09:30 PM PDT 24
Peak memory 206120 kb
Host smart-7108924c-bf0c-41ea-98e2-61a440834449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303856688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2303856688
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3047038004
Short name T448
Test name
Test status
Simulation time 211734267 ps
CPU time 0.82 seconds
Started Jun 22 06:09:27 PM PDT 24
Finished Jun 22 06:09:28 PM PDT 24
Peak memory 206096 kb
Host smart-e930148e-15d6-4d08-94d9-d32a9120c1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047038004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3047038004
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.317583486
Short name T257
Test name
Test status
Simulation time 1999540595 ps
CPU time 4.1 seconds
Started Jun 22 06:09:34 PM PDT 24
Finished Jun 22 06:09:39 PM PDT 24
Peak memory 232768 kb
Host smart-dc0452c2-fd55-451e-ab94-36a6546495bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317583486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.317583486
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1912904118
Short name T438
Test name
Test status
Simulation time 12685190 ps
CPU time 0.78 seconds
Started Jun 22 06:10:37 PM PDT 24
Finished Jun 22 06:10:38 PM PDT 24
Peak memory 205456 kb
Host smart-df311501-4ec0-4c0d-a61f-562e46d82a66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912904118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1912904118
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3261593130
Short name T456
Test name
Test status
Simulation time 171766565 ps
CPU time 3.29 seconds
Started Jun 22 06:10:36 PM PDT 24
Finished Jun 22 06:10:40 PM PDT 24
Peak memory 232900 kb
Host smart-4d5d86f6-5bb8-47e1-bfd0-89c4752d90e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261593130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3261593130
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1962065407
Short name T73
Test name
Test status
Simulation time 40121197 ps
CPU time 0.81 seconds
Started Jun 22 06:10:37 PM PDT 24
Finished Jun 22 06:10:38 PM PDT 24
Peak memory 206728 kb
Host smart-e8afc013-26b3-4c05-ba96-563c316851b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962065407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1962065407
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2890342946
Short name T512
Test name
Test status
Simulation time 22715426295 ps
CPU time 106.87 seconds
Started Jun 22 06:10:39 PM PDT 24
Finished Jun 22 06:12:27 PM PDT 24
Peak memory 249604 kb
Host smart-47706aa6-6832-4b66-974c-952da9973b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890342946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2890342946
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3001827183
Short name T146
Test name
Test status
Simulation time 31190497908 ps
CPU time 369.49 seconds
Started Jun 22 06:10:38 PM PDT 24
Finished Jun 22 06:16:48 PM PDT 24
Peak memory 266360 kb
Host smart-e13a0f4c-1f1d-43ce-af86-8082da3fc721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001827183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3001827183
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2565870201
Short name T809
Test name
Test status
Simulation time 306284075 ps
CPU time 7.78 seconds
Started Jun 22 06:10:39 PM PDT 24
Finished Jun 22 06:10:47 PM PDT 24
Peak memory 236536 kb
Host smart-9d954f31-e1c2-4345-81c7-5ed45e5565b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565870201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2565870201
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3464523766
Short name T202
Test name
Test status
Simulation time 14572812322 ps
CPU time 30.6 seconds
Started Jun 22 06:10:36 PM PDT 24
Finished Jun 22 06:11:08 PM PDT 24
Peak memory 233012 kb
Host smart-34bae70d-956a-49e1-8bf1-d8d9d549d8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464523766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3464523766
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4217833542
Short name T691
Test name
Test status
Simulation time 31540176560 ps
CPU time 79.03 seconds
Started Jun 22 06:10:39 PM PDT 24
Finished Jun 22 06:11:58 PM PDT 24
Peak memory 224768 kb
Host smart-c61fbb73-0b0e-4533-9df3-bad77e908aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217833542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4217833542
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1154726166
Short name T473
Test name
Test status
Simulation time 1781741998 ps
CPU time 5.61 seconds
Started Jun 22 06:10:39 PM PDT 24
Finished Jun 22 06:10:45 PM PDT 24
Peak memory 224620 kb
Host smart-3d4f5f2a-5f6a-4522-9598-9a3174e40359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154726166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1154726166
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.4094463078
Short name T275
Test name
Test status
Simulation time 592554587 ps
CPU time 7.66 seconds
Started Jun 22 06:10:36 PM PDT 24
Finished Jun 22 06:10:45 PM PDT 24
Peak memory 240944 kb
Host smart-4e09386e-83ce-4912-b343-f07a7844b91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094463078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4094463078
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3084483501
Short name T842
Test name
Test status
Simulation time 1126587669 ps
CPU time 8.84 seconds
Started Jun 22 06:10:36 PM PDT 24
Finished Jun 22 06:10:46 PM PDT 24
Peak memory 222180 kb
Host smart-99289b27-b79a-4081-b861-41fceb29e19c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3084483501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3084483501
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.716053919
Short name T412
Test name
Test status
Simulation time 201109814 ps
CPU time 0.97 seconds
Started Jun 22 06:10:37 PM PDT 24
Finished Jun 22 06:10:39 PM PDT 24
Peak memory 207016 kb
Host smart-7bf60ea3-d901-4e1c-803f-555b37a5f40d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716053919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.716053919
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1344451556
Short name T343
Test name
Test status
Simulation time 870880868 ps
CPU time 2.96 seconds
Started Jun 22 06:10:37 PM PDT 24
Finished Jun 22 06:10:41 PM PDT 24
Peak memory 216452 kb
Host smart-46d86c7c-6564-49eb-a74f-7a21e88fbe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344451556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1344451556
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1432303905
Short name T407
Test name
Test status
Simulation time 233338531 ps
CPU time 1.34 seconds
Started Jun 22 06:10:37 PM PDT 24
Finished Jun 22 06:10:39 PM PDT 24
Peak memory 207932 kb
Host smart-633c3c89-5b1a-4d89-8c0a-62deaa6d71b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432303905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1432303905
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3611951160
Short name T733
Test name
Test status
Simulation time 25571422 ps
CPU time 0.98 seconds
Started Jun 22 06:10:36 PM PDT 24
Finished Jun 22 06:10:38 PM PDT 24
Peak memory 208080 kb
Host smart-a28642cf-e341-4a60-82ee-899132adfb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611951160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3611951160
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2268490170
Short name T772
Test name
Test status
Simulation time 33042542 ps
CPU time 0.86 seconds
Started Jun 22 06:10:38 PM PDT 24
Finished Jun 22 06:10:40 PM PDT 24
Peak memory 206100 kb
Host smart-2f3792a3-97e8-4b8e-8799-c151091478c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268490170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2268490170
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2311150804
Short name T253
Test name
Test status
Simulation time 276325268 ps
CPU time 3.35 seconds
Started Jun 22 06:10:42 PM PDT 24
Finished Jun 22 06:10:46 PM PDT 24
Peak memory 224636 kb
Host smart-33a453a5-7e04-46e4-ba67-a9ba0c377673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311150804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2311150804
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1393928500
Short name T734
Test name
Test status
Simulation time 15671957 ps
CPU time 0.73 seconds
Started Jun 22 06:10:42 PM PDT 24
Finished Jun 22 06:10:44 PM PDT 24
Peak memory 205528 kb
Host smart-ea01f16d-3e99-410b-9451-e3a5bee646a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393928500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1393928500
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2829159744
Short name T373
Test name
Test status
Simulation time 92651239 ps
CPU time 2.99 seconds
Started Jun 22 06:10:37 PM PDT 24
Finished Jun 22 06:10:41 PM PDT 24
Peak memory 232876 kb
Host smart-adfb057e-f7d2-4777-86e8-bc6b7d785d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829159744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2829159744
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.623681405
Short name T817
Test name
Test status
Simulation time 20470685 ps
CPU time 0.78 seconds
Started Jun 22 06:10:40 PM PDT 24
Finished Jun 22 06:10:41 PM PDT 24
Peak memory 206868 kb
Host smart-1cf9f33a-2b2d-403f-b00d-d1b2e559667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623681405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.623681405
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3152802863
Short name T379
Test name
Test status
Simulation time 13457024233 ps
CPU time 90.29 seconds
Started Jun 22 06:10:40 PM PDT 24
Finished Jun 22 06:12:11 PM PDT 24
Peak memory 265324 kb
Host smart-b2441f51-b285-4d8e-93ef-d29449aad929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152802863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3152802863
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.4274676544
Short name T591
Test name
Test status
Simulation time 10688656253 ps
CPU time 99.64 seconds
Started Jun 22 06:10:45 PM PDT 24
Finished Jun 22 06:12:26 PM PDT 24
Peak memory 252500 kb
Host smart-7fb1a14d-a57e-443d-950b-d80fc89cc11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274676544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.4274676544
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3062132694
Short name T226
Test name
Test status
Simulation time 6807825701 ps
CPU time 108.56 seconds
Started Jun 22 06:10:42 PM PDT 24
Finished Jun 22 06:12:32 PM PDT 24
Peak memory 265692 kb
Host smart-7b116aeb-2fd4-4ff0-bedd-833dfe7eea5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062132694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3062132694
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.617270744
Short name T613
Test name
Test status
Simulation time 930741690 ps
CPU time 6.62 seconds
Started Jun 22 06:10:38 PM PDT 24
Finished Jun 22 06:10:45 PM PDT 24
Peak memory 224800 kb
Host smart-8198a911-8695-49d0-8a3c-7e0e5be0cf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617270744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.617270744
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2268538584
Short name T547
Test name
Test status
Simulation time 1345789935 ps
CPU time 6.22 seconds
Started Jun 22 06:10:45 PM PDT 24
Finished Jun 22 06:10:52 PM PDT 24
Peak memory 232888 kb
Host smart-7bcab894-5269-4d6f-8211-72c1bc9dd9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268538584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2268538584
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1526498747
Short name T879
Test name
Test status
Simulation time 1275229044 ps
CPU time 4.27 seconds
Started Jun 22 06:10:45 PM PDT 24
Finished Jun 22 06:10:50 PM PDT 24
Peak memory 224672 kb
Host smart-640f4367-23e5-426f-892c-37f7c9c5be1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526498747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1526498747
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2778109706
Short name T619
Test name
Test status
Simulation time 116329326 ps
CPU time 2.55 seconds
Started Jun 22 06:10:44 PM PDT 24
Finished Jun 22 06:10:48 PM PDT 24
Peak memory 232852 kb
Host smart-de18337b-bdac-4c18-ab4d-e0fe654ff944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778109706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2778109706
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3351967613
Short name T70
Test name
Test status
Simulation time 2461334360 ps
CPU time 11.15 seconds
Started Jun 22 06:10:37 PM PDT 24
Finished Jun 22 06:10:49 PM PDT 24
Peak memory 232968 kb
Host smart-888107b5-dbd3-483c-a6ec-7b8e71fd914b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351967613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3351967613
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1826865061
Short name T762
Test name
Test status
Simulation time 626127835 ps
CPU time 4.02 seconds
Started Jun 22 06:10:36 PM PDT 24
Finished Jun 22 06:10:40 PM PDT 24
Peak memory 219576 kb
Host smart-e3b265ee-59c6-4d4c-8869-53649e023cfc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1826865061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1826865061
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3151289660
Short name T166
Test name
Test status
Simulation time 29378028833 ps
CPU time 209.84 seconds
Started Jun 22 06:10:53 PM PDT 24
Finished Jun 22 06:14:24 PM PDT 24
Peak memory 271520 kb
Host smart-8217581e-42b5-4e20-8c1c-d3a9c5a6837f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151289660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3151289660
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1496736826
Short name T575
Test name
Test status
Simulation time 339716600 ps
CPU time 3.26 seconds
Started Jun 22 06:10:38 PM PDT 24
Finished Jun 22 06:10:42 PM PDT 24
Peak memory 218688 kb
Host smart-884cc66c-502f-44df-ba47-f8c2ddd0cde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496736826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1496736826
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.891628089
Short name T704
Test name
Test status
Simulation time 13613428711 ps
CPU time 20.46 seconds
Started Jun 22 06:10:36 PM PDT 24
Finished Jun 22 06:10:57 PM PDT 24
Peak memory 216504 kb
Host smart-75fa3842-3630-4109-a443-17e9896c82aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891628089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.891628089
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.254060806
Short name T708
Test name
Test status
Simulation time 29599364 ps
CPU time 1.62 seconds
Started Jun 22 06:10:37 PM PDT 24
Finished Jun 22 06:10:39 PM PDT 24
Peak memory 216388 kb
Host smart-8acbc717-93bd-4d1d-bd67-f988ab1d55ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254060806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.254060806
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.796820149
Short name T697
Test name
Test status
Simulation time 15851897 ps
CPU time 0.68 seconds
Started Jun 22 06:10:45 PM PDT 24
Finished Jun 22 06:10:47 PM PDT 24
Peak memory 205696 kb
Host smart-4993df62-137a-4765-8bdf-402454396df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796820149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.796820149
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3834043437
Short name T758
Test name
Test status
Simulation time 1093704481 ps
CPU time 4.93 seconds
Started Jun 22 06:10:38 PM PDT 24
Finished Jun 22 06:10:43 PM PDT 24
Peak memory 224668 kb
Host smart-0ff74293-2bf5-4e1e-91f5-bf0e6de649a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834043437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3834043437
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1705094692
Short name T844
Test name
Test status
Simulation time 40213817 ps
CPU time 0.68 seconds
Started Jun 22 06:10:45 PM PDT 24
Finished Jun 22 06:10:47 PM PDT 24
Peak memory 204936 kb
Host smart-3aa9a9be-8990-42f3-ab2c-25ebd0de0b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705094692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1705094692
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3671993546
Short name T51
Test name
Test status
Simulation time 33636546 ps
CPU time 2.16 seconds
Started Jun 22 06:10:53 PM PDT 24
Finished Jun 22 06:10:56 PM PDT 24
Peak memory 224644 kb
Host smart-5eb1c2a4-5197-40f9-82f8-d7c6ed321ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671993546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3671993546
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3683139283
Short name T453
Test name
Test status
Simulation time 104344426 ps
CPU time 0.8 seconds
Started Jun 22 06:10:43 PM PDT 24
Finished Jun 22 06:10:45 PM PDT 24
Peak memory 206720 kb
Host smart-ca546c9b-4ca6-42b0-a2a7-84dad4b4a2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683139283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3683139283
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3729047979
Short name T303
Test name
Test status
Simulation time 55890937398 ps
CPU time 219.48 seconds
Started Jun 22 06:10:43 PM PDT 24
Finished Jun 22 06:14:24 PM PDT 24
Peak memory 249400 kb
Host smart-8336f51f-633d-463d-ba53-5df27febbb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729047979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3729047979
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1405468289
Short name T425
Test name
Test status
Simulation time 2000621409 ps
CPU time 19.94 seconds
Started Jun 22 06:10:42 PM PDT 24
Finished Jun 22 06:11:02 PM PDT 24
Peak memory 224616 kb
Host smart-6894a600-d8d1-4f1f-bb93-456481a18b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405468289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1405468289
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1020710369
Short name T837
Test name
Test status
Simulation time 14384758653 ps
CPU time 111.02 seconds
Started Jun 22 06:10:53 PM PDT 24
Finished Jun 22 06:12:45 PM PDT 24
Peak memory 233056 kb
Host smart-0d3abac7-8a6b-4145-abd2-9785ae709c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020710369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1020710369
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.12482983
Short name T804
Test name
Test status
Simulation time 484310338 ps
CPU time 4.05 seconds
Started Jun 22 06:10:47 PM PDT 24
Finished Jun 22 06:10:52 PM PDT 24
Peak memory 218940 kb
Host smart-5f103533-c3bf-4f5c-8539-cf2d919be599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12482983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.12482983
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2544985587
Short name T5
Test name
Test status
Simulation time 606063708 ps
CPU time 3.26 seconds
Started Jun 22 06:10:43 PM PDT 24
Finished Jun 22 06:10:47 PM PDT 24
Peak memory 224644 kb
Host smart-cd31c71d-7844-4bf5-8ef6-2e727e2d723a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544985587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2544985587
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.529479886
Short name T215
Test name
Test status
Simulation time 2658871617 ps
CPU time 20.19 seconds
Started Jun 22 06:10:42 PM PDT 24
Finished Jun 22 06:11:04 PM PDT 24
Peak memory 232908 kb
Host smart-0410c8dd-0f1f-406b-bf49-d9d8c26f5a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529479886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.529479886
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.599093727
Short name T375
Test name
Test status
Simulation time 361569550 ps
CPU time 5.08 seconds
Started Jun 22 06:10:47 PM PDT 24
Finished Jun 22 06:10:53 PM PDT 24
Peak memory 232840 kb
Host smart-84930af3-d600-4fe0-a3a2-b2aab646a5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599093727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.599093727
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1246136330
Short name T139
Test name
Test status
Simulation time 7120406990 ps
CPU time 23.47 seconds
Started Jun 22 06:10:44 PM PDT 24
Finished Jun 22 06:11:09 PM PDT 24
Peak memory 224780 kb
Host smart-80c0c521-16cc-46e4-9ffe-4a63018b2cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246136330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1246136330
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3387038985
Short name T572
Test name
Test status
Simulation time 1221330475 ps
CPU time 3.85 seconds
Started Jun 22 06:10:45 PM PDT 24
Finished Jun 22 06:10:50 PM PDT 24
Peak memory 223140 kb
Host smart-feb8d6d8-9322-4b4a-8a1e-59f62c3a4636
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3387038985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3387038985
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.900202298
Short name T624
Test name
Test status
Simulation time 16616175648 ps
CPU time 120.34 seconds
Started Jun 22 06:10:47 PM PDT 24
Finished Jun 22 06:12:48 PM PDT 24
Peak memory 254540 kb
Host smart-34b38496-e9e6-4caf-97c3-c655da921425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900202298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.900202298
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1032310868
Short name T66
Test name
Test status
Simulation time 31785168 ps
CPU time 0.76 seconds
Started Jun 22 06:10:47 PM PDT 24
Finished Jun 22 06:10:48 PM PDT 24
Peak memory 205792 kb
Host smart-c8d21932-93e1-4518-b732-fed17c9e6db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032310868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1032310868
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2823701620
Short name T388
Test name
Test status
Simulation time 170550216 ps
CPU time 1.86 seconds
Started Jun 22 06:10:44 PM PDT 24
Finished Jun 22 06:10:46 PM PDT 24
Peak memory 216296 kb
Host smart-171159e3-75cc-49d7-b685-2f81f1949092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823701620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2823701620
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1594758577
Short name T440
Test name
Test status
Simulation time 250549229 ps
CPU time 2.49 seconds
Started Jun 22 06:10:44 PM PDT 24
Finished Jun 22 06:10:47 PM PDT 24
Peak memory 216396 kb
Host smart-fc1ccb51-f028-425a-b27e-c8b278a417f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594758577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1594758577
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3027957515
Short name T451
Test name
Test status
Simulation time 123286114 ps
CPU time 0.85 seconds
Started Jun 22 06:10:49 PM PDT 24
Finished Jun 22 06:10:50 PM PDT 24
Peak memory 206096 kb
Host smart-6e5340ae-f85f-467e-844f-2c89fc76b49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027957515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3027957515
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3820321203
Short name T555
Test name
Test status
Simulation time 5763294044 ps
CPU time 9.5 seconds
Started Jun 22 06:10:42 PM PDT 24
Finished Jun 22 06:10:53 PM PDT 24
Peak memory 232988 kb
Host smart-a37943d4-1023-4279-93d2-e16d0d16791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820321203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3820321203
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1485966014
Short name T491
Test name
Test status
Simulation time 36469074 ps
CPU time 0.72 seconds
Started Jun 22 06:10:51 PM PDT 24
Finished Jun 22 06:10:52 PM PDT 24
Peak memory 205420 kb
Host smart-3a45e130-14a0-42ed-8a06-91965201e8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485966014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1485966014
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1707140579
Short name T505
Test name
Test status
Simulation time 72184778 ps
CPU time 2.92 seconds
Started Jun 22 06:10:42 PM PDT 24
Finished Jun 22 06:10:47 PM PDT 24
Peak memory 232856 kb
Host smart-965c5c33-c03f-4490-b4b8-7470b085d12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707140579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1707140579
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2853667282
Short name T877
Test name
Test status
Simulation time 23105111 ps
CPU time 0.75 seconds
Started Jun 22 06:10:43 PM PDT 24
Finished Jun 22 06:10:45 PM PDT 24
Peak memory 207068 kb
Host smart-2cf0fade-ff7a-410c-ad0f-1635d9a42ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853667282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2853667282
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2597445706
Short name T428
Test name
Test status
Simulation time 34425263 ps
CPU time 0.78 seconds
Started Jun 22 06:10:47 PM PDT 24
Finished Jun 22 06:10:49 PM PDT 24
Peak memory 215980 kb
Host smart-acaf0365-2c06-491a-a8f8-a57c30e15313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597445706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2597445706
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3176313302
Short name T221
Test name
Test status
Simulation time 24857348261 ps
CPU time 112.15 seconds
Started Jun 22 06:10:47 PM PDT 24
Finished Jun 22 06:12:40 PM PDT 24
Peak memory 241156 kb
Host smart-495b5d97-e1c3-44a0-9dff-65c7f419f188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176313302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3176313302
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3769562908
Short name T662
Test name
Test status
Simulation time 1910818110 ps
CPU time 23.91 seconds
Started Jun 22 06:10:49 PM PDT 24
Finished Jun 22 06:11:14 PM PDT 24
Peak memory 224632 kb
Host smart-4f595d74-50aa-4da2-80e7-41cb2bc87e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769562908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3769562908
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1489933777
Short name T264
Test name
Test status
Simulation time 380832635 ps
CPU time 2.38 seconds
Started Jun 22 06:10:48 PM PDT 24
Finished Jun 22 06:10:51 PM PDT 24
Peak memory 224632 kb
Host smart-d416b238-c805-4faa-acf7-ee5d6ec97f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489933777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1489933777
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1171968613
Short name T504
Test name
Test status
Simulation time 3558001118 ps
CPU time 42.6 seconds
Started Jun 22 06:10:47 PM PDT 24
Finished Jun 22 06:11:31 PM PDT 24
Peak memory 238184 kb
Host smart-40854173-3c76-4cf0-ad33-e21b8523354a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171968613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1171968613
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.309693173
Short name T941
Test name
Test status
Simulation time 1095424804 ps
CPU time 4.76 seconds
Started Jun 22 06:10:47 PM PDT 24
Finished Jun 22 06:10:52 PM PDT 24
Peak memory 232824 kb
Host smart-15d02544-5019-4760-b04c-9ad3ca5d0013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309693173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.309693173
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.834501464
Short name T244
Test name
Test status
Simulation time 12678466131 ps
CPU time 17.39 seconds
Started Jun 22 06:10:43 PM PDT 24
Finished Jun 22 06:11:01 PM PDT 24
Peak memory 241100 kb
Host smart-d6ff7411-0158-475a-b44d-afe29ea69660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834501464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.834501464
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3255523694
Short name T903
Test name
Test status
Simulation time 1675559388 ps
CPU time 7.69 seconds
Started Jun 22 06:10:53 PM PDT 24
Finished Jun 22 06:11:01 PM PDT 24
Peak memory 222320 kb
Host smart-05c399dd-905d-47b7-a3a5-86065e265bda
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3255523694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3255523694
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.99406626
Short name T414
Test name
Test status
Simulation time 227848278378 ps
CPU time 302.59 seconds
Started Jun 22 06:10:53 PM PDT 24
Finished Jun 22 06:15:56 PM PDT 24
Peak memory 253440 kb
Host smart-ab863edf-a88b-4fbd-ad7b-4bcba647d68e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99406626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress
_all.99406626
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3939808108
Short name T793
Test name
Test status
Simulation time 474303051 ps
CPU time 6.53 seconds
Started Jun 22 06:10:53 PM PDT 24
Finished Jun 22 06:11:00 PM PDT 24
Peak memory 216676 kb
Host smart-c60be410-22ec-4f12-9969-cc961647749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939808108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3939808108
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2769502814
Short name T71
Test name
Test status
Simulation time 76242795 ps
CPU time 1.07 seconds
Started Jun 22 06:10:44 PM PDT 24
Finished Jun 22 06:10:46 PM PDT 24
Peak memory 206268 kb
Host smart-1aa7cf78-3cee-4040-8ca2-440c342f5b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769502814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2769502814
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2156377072
Short name T771
Test name
Test status
Simulation time 35780306 ps
CPU time 0.89 seconds
Started Jun 22 06:10:47 PM PDT 24
Finished Jun 22 06:10:49 PM PDT 24
Peak memory 207148 kb
Host smart-c0ec674d-8dc1-44dd-847f-c30c1ecb0401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156377072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2156377072
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2825759479
Short name T833
Test name
Test status
Simulation time 148676039 ps
CPU time 0.81 seconds
Started Jun 22 06:10:45 PM PDT 24
Finished Jun 22 06:10:47 PM PDT 24
Peak memory 206100 kb
Host smart-2f6a61c8-e590-426b-853d-73b4ce27618a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825759479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2825759479
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2002503999
Short name T950
Test name
Test status
Simulation time 395181260 ps
CPU time 3.82 seconds
Started Jun 22 06:10:44 PM PDT 24
Finished Jun 22 06:10:49 PM PDT 24
Peak memory 224640 kb
Host smart-6fd38ced-8658-4514-add7-68ee23a41572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002503999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2002503999
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2234954863
Short name T853
Test name
Test status
Simulation time 91792956 ps
CPU time 0.69 seconds
Started Jun 22 06:10:50 PM PDT 24
Finished Jun 22 06:10:52 PM PDT 24
Peak memory 204824 kb
Host smart-82deb00f-5dc1-4198-b6e0-a9d258590d1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234954863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2234954863
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2416734679
Short name T635
Test name
Test status
Simulation time 551251915 ps
CPU time 6.5 seconds
Started Jun 22 06:10:51 PM PDT 24
Finished Jun 22 06:10:58 PM PDT 24
Peak memory 224624 kb
Host smart-d9590596-da2c-42c0-b8ae-04a18213d5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416734679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2416734679
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2932864600
Short name T351
Test name
Test status
Simulation time 190594520 ps
CPU time 0.79 seconds
Started Jun 22 06:10:54 PM PDT 24
Finished Jun 22 06:10:55 PM PDT 24
Peak memory 206708 kb
Host smart-a4c5cb89-e25f-4904-bb7c-97507cc147e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932864600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2932864600
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.914656389
Short name T827
Test name
Test status
Simulation time 585586139 ps
CPU time 14.73 seconds
Started Jun 22 06:10:51 PM PDT 24
Finished Jun 22 06:11:07 PM PDT 24
Peak memory 224636 kb
Host smart-cf23904d-2dfe-447b-ad06-4ca37fae0a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914656389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.914656389
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4281055700
Short name T439
Test name
Test status
Simulation time 6787114706 ps
CPU time 15.11 seconds
Started Jun 22 06:10:52 PM PDT 24
Finished Jun 22 06:11:07 PM PDT 24
Peak memory 224780 kb
Host smart-e2fe4a95-9f66-4604-a6d9-b737d0d2661a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281055700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4281055700
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.949775724
Short name T471
Test name
Test status
Simulation time 199033861 ps
CPU time 2.04 seconds
Started Jun 22 06:10:49 PM PDT 24
Finished Jun 22 06:10:51 PM PDT 24
Peak memory 223132 kb
Host smart-152f3a8c-5eba-4b23-8d2b-6d04bbffe523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949775724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.949775724
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.947538326
Short name T267
Test name
Test status
Simulation time 10796902598 ps
CPU time 14.56 seconds
Started Jun 22 06:10:49 PM PDT 24
Finished Jun 22 06:11:04 PM PDT 24
Peak memory 248756 kb
Host smart-43463d78-fdbc-497d-98e3-2e5d0ce7a2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947538326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.947538326
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1120483329
Short name T391
Test name
Test status
Simulation time 35765417315 ps
CPU time 14.8 seconds
Started Jun 22 06:10:52 PM PDT 24
Finished Jun 22 06:11:07 PM PDT 24
Peak memory 233016 kb
Host smart-1449dd4a-d14e-4238-a329-b492b2245f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120483329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1120483329
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2859029394
Short name T642
Test name
Test status
Simulation time 553953334 ps
CPU time 5.9 seconds
Started Jun 22 06:10:48 PM PDT 24
Finished Jun 22 06:10:55 PM PDT 24
Peak memory 221240 kb
Host smart-7bfda3df-63aa-48c9-bcbb-f168d0d92d80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2859029394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2859029394
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3651212054
Short name T20
Test name
Test status
Simulation time 79201757608 ps
CPU time 35.73 seconds
Started Jun 22 06:10:56 PM PDT 24
Finished Jun 22 06:11:32 PM PDT 24
Peak memory 224764 kb
Host smart-d1d5d12d-f250-4ca4-a029-50f0bbff98d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651212054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3651212054
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.836704491
Short name T321
Test name
Test status
Simulation time 1950058504 ps
CPU time 10.43 seconds
Started Jun 22 06:10:50 PM PDT 24
Finished Jun 22 06:11:01 PM PDT 24
Peak memory 216396 kb
Host smart-3d3c5205-aeea-424c-8c6f-d3f33d859a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836704491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.836704491
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3166235876
Short name T868
Test name
Test status
Simulation time 5054930279 ps
CPU time 15.41 seconds
Started Jun 22 06:10:50 PM PDT 24
Finished Jun 22 06:11:06 PM PDT 24
Peak memory 216480 kb
Host smart-9214e182-5e06-4ebe-a59a-7636d03e1299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166235876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3166235876
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2282456443
Short name T626
Test name
Test status
Simulation time 75011895 ps
CPU time 0.84 seconds
Started Jun 22 06:10:49 PM PDT 24
Finished Jun 22 06:10:51 PM PDT 24
Peak memory 206132 kb
Host smart-c3caccf6-2015-4e41-b853-62689e85f088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282456443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2282456443
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2477118020
Short name T620
Test name
Test status
Simulation time 318959091 ps
CPU time 0.95 seconds
Started Jun 22 06:10:50 PM PDT 24
Finished Jun 22 06:10:52 PM PDT 24
Peak memory 207120 kb
Host smart-9efdf40b-da8b-4ebb-9984-63df44a9fb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477118020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2477118020
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3380826533
Short name T775
Test name
Test status
Simulation time 22211635457 ps
CPU time 30.08 seconds
Started Jun 22 06:10:53 PM PDT 24
Finished Jun 22 06:11:24 PM PDT 24
Peak memory 239824 kb
Host smart-08728814-82ff-4c06-b431-21980eca4e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380826533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3380826533
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1470520504
Short name T346
Test name
Test status
Simulation time 14442398 ps
CPU time 0.78 seconds
Started Jun 22 06:10:59 PM PDT 24
Finished Jun 22 06:11:01 PM PDT 24
Peak memory 205476 kb
Host smart-08ec1af7-786d-4bd5-94a6-69b8254a80d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470520504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1470520504
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1455361416
Short name T383
Test name
Test status
Simulation time 1471434888 ps
CPU time 6.96 seconds
Started Jun 22 06:10:58 PM PDT 24
Finished Jun 22 06:11:06 PM PDT 24
Peak memory 232780 kb
Host smart-74856814-0c52-41ad-968c-17eb407d3c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455361416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1455361416
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.844004384
Short name T589
Test name
Test status
Simulation time 20950798 ps
CPU time 0.79 seconds
Started Jun 22 06:10:55 PM PDT 24
Finished Jun 22 06:10:56 PM PDT 24
Peak memory 207068 kb
Host smart-97f8f894-bd1b-42ab-95cd-81f58ffd3db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844004384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.844004384
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.976818539
Short name T305
Test name
Test status
Simulation time 9918591578 ps
CPU time 100.3 seconds
Started Jun 22 06:10:58 PM PDT 24
Finished Jun 22 06:12:40 PM PDT 24
Peak memory 264156 kb
Host smart-20b0a5ae-113e-47b0-b7ca-d39876851fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976818539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.976818539
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2518455913
Short name T605
Test name
Test status
Simulation time 25169370647 ps
CPU time 149.2 seconds
Started Jun 22 06:10:56 PM PDT 24
Finished Jun 22 06:13:26 PM PDT 24
Peak memory 267376 kb
Host smart-b50b4ef0-187a-48d7-95aa-ae645896a997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518455913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2518455913
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.968372703
Short name T149
Test name
Test status
Simulation time 16710301548 ps
CPU time 154.78 seconds
Started Jun 22 06:10:57 PM PDT 24
Finished Jun 22 06:13:33 PM PDT 24
Peak memory 265604 kb
Host smart-4d5ff8b2-ad5b-4612-804e-80d0cceb0ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968372703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.968372703
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.737002093
Short name T364
Test name
Test status
Simulation time 151968270 ps
CPU time 4.8 seconds
Started Jun 22 06:10:57 PM PDT 24
Finished Jun 22 06:11:02 PM PDT 24
Peak memory 224688 kb
Host smart-4073eabf-1df6-49ee-bd5d-2d18fef76216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737002093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.737002093
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.785580817
Short name T94
Test name
Test status
Simulation time 350721399 ps
CPU time 8.39 seconds
Started Jun 22 06:10:58 PM PDT 24
Finished Jun 22 06:11:07 PM PDT 24
Peak memory 224612 kb
Host smart-9a8fecbd-58a2-4393-a25f-d5af04a0eab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785580817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.785580817
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3846692991
Short name T937
Test name
Test status
Simulation time 503401564 ps
CPU time 10.04 seconds
Started Jun 22 06:10:56 PM PDT 24
Finished Jun 22 06:11:07 PM PDT 24
Peak memory 249192 kb
Host smart-64bcda10-548a-426a-9aa5-ae12cf98f1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846692991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3846692991
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.77351354
Short name T8
Test name
Test status
Simulation time 124317433 ps
CPU time 2.92 seconds
Started Jun 22 06:10:55 PM PDT 24
Finished Jun 22 06:10:59 PM PDT 24
Peak memory 232832 kb
Host smart-e1af8990-dfbf-4fff-a66a-67541dafd6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77351354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.77351354
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3179677759
Short name T710
Test name
Test status
Simulation time 34868802 ps
CPU time 2.19 seconds
Started Jun 22 06:10:56 PM PDT 24
Finished Jun 22 06:10:59 PM PDT 24
Peak memory 232572 kb
Host smart-829f214f-5c09-4f94-a22e-a6b23a4d8589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179677759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3179677759
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2998025243
Short name T932
Test name
Test status
Simulation time 7261447764 ps
CPU time 9.84 seconds
Started Jun 22 06:10:57 PM PDT 24
Finished Jun 22 06:11:08 PM PDT 24
Peak memory 219172 kb
Host smart-0caf3bc5-2ba0-44aa-bacc-9e6b3d5f6131
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2998025243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2998025243
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.733853127
Short name T928
Test name
Test status
Simulation time 21391959547 ps
CPU time 26.8 seconds
Started Jun 22 06:10:52 PM PDT 24
Finished Jun 22 06:11:20 PM PDT 24
Peak memory 216568 kb
Host smart-9518799b-a142-4f90-94f4-7cb8240a2a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733853127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.733853127
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.644123283
Short name T91
Test name
Test status
Simulation time 291527591 ps
CPU time 1.46 seconds
Started Jun 22 06:10:52 PM PDT 24
Finished Jun 22 06:10:54 PM PDT 24
Peak memory 208084 kb
Host smart-382628bb-673a-40a6-8652-fa624a52640c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644123283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.644123283
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3708801211
Short name T922
Test name
Test status
Simulation time 11402391 ps
CPU time 0.7 seconds
Started Jun 22 06:10:58 PM PDT 24
Finished Jun 22 06:11:00 PM PDT 24
Peak memory 205688 kb
Host smart-71f53003-1c95-455f-bf48-97545d629d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708801211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3708801211
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1541536062
Short name T541
Test name
Test status
Simulation time 23004902 ps
CPU time 0.76 seconds
Started Jun 22 06:10:50 PM PDT 24
Finished Jun 22 06:10:52 PM PDT 24
Peak memory 206092 kb
Host smart-33c342d7-d6f5-43cd-83c1-9bcae4816ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541536062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1541536062
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2200972602
Short name T404
Test name
Test status
Simulation time 492289988 ps
CPU time 4.05 seconds
Started Jun 22 06:10:58 PM PDT 24
Finished Jun 22 06:11:03 PM PDT 24
Peak memory 232892 kb
Host smart-5479d180-d52d-4c74-b000-ddf09a7d60f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200972602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2200972602
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.181026922
Short name T345
Test name
Test status
Simulation time 78762086 ps
CPU time 0.71 seconds
Started Jun 22 06:11:03 PM PDT 24
Finished Jun 22 06:11:05 PM PDT 24
Peak memory 205532 kb
Host smart-c6958653-1c5d-4ec1-969c-bb072d48a83d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181026922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.181026922
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3338056367
Short name T769
Test name
Test status
Simulation time 251835105 ps
CPU time 2.79 seconds
Started Jun 22 06:11:00 PM PDT 24
Finished Jun 22 06:11:03 PM PDT 24
Peak memory 232492 kb
Host smart-2d2a8aa6-7da3-40c3-94d5-9f1566a7fc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338056367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3338056367
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1113034745
Short name T168
Test name
Test status
Simulation time 26597519 ps
CPU time 0.8 seconds
Started Jun 22 06:10:57 PM PDT 24
Finished Jun 22 06:10:58 PM PDT 24
Peak memory 206744 kb
Host smart-3f797406-f279-4fb9-a3cd-0df2eb8a9f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113034745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1113034745
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2813840362
Short name T401
Test name
Test status
Simulation time 2227961812 ps
CPU time 24.68 seconds
Started Jun 22 06:10:56 PM PDT 24
Finished Jun 22 06:11:22 PM PDT 24
Peak memory 239592 kb
Host smart-6824cb5d-0da4-4469-8b22-88d23ba5455b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813840362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2813840362
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2537491919
Short name T304
Test name
Test status
Simulation time 7898767782 ps
CPU time 122.51 seconds
Started Jun 22 06:10:59 PM PDT 24
Finished Jun 22 06:13:02 PM PDT 24
Peak memory 255732 kb
Host smart-cc6d538b-bc07-4eea-aef1-6394574bc05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537491919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2537491919
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2871235983
Short name T735
Test name
Test status
Simulation time 3983735094 ps
CPU time 76.81 seconds
Started Jun 22 06:11:05 PM PDT 24
Finished Jun 22 06:12:23 PM PDT 24
Peak memory 257624 kb
Host smart-5e925874-bd58-4f26-822a-6bc18f00f995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871235983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2871235983
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3900378527
Short name T309
Test name
Test status
Simulation time 753469587 ps
CPU time 13.03 seconds
Started Jun 22 06:11:00 PM PDT 24
Finished Jun 22 06:11:13 PM PDT 24
Peak memory 232832 kb
Host smart-998aeaa5-00be-46db-afab-231f4f03fd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900378527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3900378527
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1773406821
Short name T532
Test name
Test status
Simulation time 235434062 ps
CPU time 5.37 seconds
Started Jun 22 06:10:56 PM PDT 24
Finished Jun 22 06:11:02 PM PDT 24
Peak memory 232868 kb
Host smart-53cbd983-bca7-400d-a274-e0789f0b12b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773406821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1773406821
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2872596107
Short name T577
Test name
Test status
Simulation time 1049034792 ps
CPU time 7.24 seconds
Started Jun 22 06:10:59 PM PDT 24
Finished Jun 22 06:11:07 PM PDT 24
Peak memory 224584 kb
Host smart-017bbd4f-47ce-41b0-b526-0761681c6232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872596107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2872596107
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4251506254
Short name T390
Test name
Test status
Simulation time 5358847615 ps
CPU time 7.47 seconds
Started Jun 22 06:10:57 PM PDT 24
Finished Jun 22 06:11:06 PM PDT 24
Peak memory 232912 kb
Host smart-4b98c652-012f-4b51-a269-48501b2e20cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251506254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4251506254
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1878053646
Short name T260
Test name
Test status
Simulation time 13436121174 ps
CPU time 8.58 seconds
Started Jun 22 06:10:58 PM PDT 24
Finished Jun 22 06:11:08 PM PDT 24
Peak memory 232976 kb
Host smart-e07d48b1-761e-4ee0-acc0-22c4cc2a014b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878053646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1878053646
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3379932331
Short name T889
Test name
Test status
Simulation time 527735304 ps
CPU time 4.8 seconds
Started Jun 22 06:10:58 PM PDT 24
Finished Jun 22 06:11:04 PM PDT 24
Peak memory 223452 kb
Host smart-5c632647-7a8e-43c1-914e-d2b1cc254e50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3379932331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3379932331
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3004881470
Short name T163
Test name
Test status
Simulation time 89838002659 ps
CPU time 238.42 seconds
Started Jun 22 06:11:04 PM PDT 24
Finished Jun 22 06:15:03 PM PDT 24
Peak memory 273152 kb
Host smart-f5896cf8-a4e7-446f-b0f0-3f8aebfce817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004881470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3004881470
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3807335597
Short name T682
Test name
Test status
Simulation time 1163851362 ps
CPU time 10.93 seconds
Started Jun 22 06:10:58 PM PDT 24
Finished Jun 22 06:11:10 PM PDT 24
Peak memory 216648 kb
Host smart-ac517df4-b6ce-4762-b595-fc202927efa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807335597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3807335597
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1472953306
Short name T525
Test name
Test status
Simulation time 6354784388 ps
CPU time 2.18 seconds
Started Jun 22 06:10:55 PM PDT 24
Finished Jun 22 06:10:58 PM PDT 24
Peak memory 216424 kb
Host smart-64201fd4-67b4-43de-b45a-e32bc654f9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472953306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1472953306
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2535286314
Short name T677
Test name
Test status
Simulation time 45958592 ps
CPU time 1.06 seconds
Started Jun 22 06:10:58 PM PDT 24
Finished Jun 22 06:11:00 PM PDT 24
Peak memory 208072 kb
Host smart-abc1fcb6-0872-43b0-b3df-c3842cd0a877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535286314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2535286314
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1647947741
Short name T724
Test name
Test status
Simulation time 235862028 ps
CPU time 0.94 seconds
Started Jun 22 06:10:59 PM PDT 24
Finished Jun 22 06:11:01 PM PDT 24
Peak memory 207124 kb
Host smart-17e33459-3a6b-4844-a154-9375ddd79f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647947741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1647947741
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1486964490
Short name T447
Test name
Test status
Simulation time 812891897 ps
CPU time 4.74 seconds
Started Jun 22 06:10:57 PM PDT 24
Finished Jun 22 06:11:03 PM PDT 24
Peak memory 232900 kb
Host smart-2216ebee-2274-4d28-91d9-da4185de4ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486964490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1486964490
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3994075303
Short name T632
Test name
Test status
Simulation time 16239619 ps
CPU time 0.75 seconds
Started Jun 22 06:11:05 PM PDT 24
Finished Jun 22 06:11:06 PM PDT 24
Peak memory 205628 kb
Host smart-43df2992-371f-4707-adea-56cded0cd74d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994075303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3994075303
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3609626483
Short name T482
Test name
Test status
Simulation time 40142502 ps
CPU time 2.73 seconds
Started Jun 22 06:11:08 PM PDT 24
Finished Jun 22 06:11:12 PM PDT 24
Peak memory 232900 kb
Host smart-f20f07a2-2bae-40cb-b685-f55df0a62598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609626483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3609626483
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1769577089
Short name T675
Test name
Test status
Simulation time 50646074 ps
CPU time 0.78 seconds
Started Jun 22 06:11:04 PM PDT 24
Finished Jun 22 06:11:05 PM PDT 24
Peak memory 205908 kb
Host smart-25144377-d884-45e8-adf7-1de260c99a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769577089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1769577089
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3295356553
Short name T2
Test name
Test status
Simulation time 6302632344 ps
CPU time 19.11 seconds
Started Jun 22 06:11:03 PM PDT 24
Finished Jun 22 06:11:23 PM PDT 24
Peak memory 249404 kb
Host smart-03855e32-332a-4c26-a264-66983436d224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295356553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3295356553
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2866329226
Short name T422
Test name
Test status
Simulation time 44555837991 ps
CPU time 85.28 seconds
Started Jun 22 06:11:09 PM PDT 24
Finished Jun 22 06:12:35 PM PDT 24
Peak memory 224848 kb
Host smart-1106deb7-c009-42de-a30e-ed75c66647ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866329226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2866329226
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2002256154
Short name T951
Test name
Test status
Simulation time 43076771 ps
CPU time 2.62 seconds
Started Jun 22 06:11:06 PM PDT 24
Finished Jun 22 06:11:09 PM PDT 24
Peak memory 232876 kb
Host smart-8e873be6-b334-4956-a407-52d6d30a11a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002256154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2002256154
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.242265271
Short name T342
Test name
Test status
Simulation time 73051415 ps
CPU time 3.33 seconds
Started Jun 22 06:11:05 PM PDT 24
Finished Jun 22 06:11:09 PM PDT 24
Peak memory 232792 kb
Host smart-50a516ef-45f8-4bc5-8703-5f3805a7dc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242265271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.242265271
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3599257599
Short name T621
Test name
Test status
Simulation time 2511773986 ps
CPU time 24.26 seconds
Started Jun 22 06:11:05 PM PDT 24
Finished Jun 22 06:11:30 PM PDT 24
Peak memory 224384 kb
Host smart-da8c0be5-e477-470b-97e7-7a336a714f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599257599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3599257599
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.124504817
Short name T299
Test name
Test status
Simulation time 975571598 ps
CPU time 6.17 seconds
Started Jun 22 06:11:02 PM PDT 24
Finished Jun 22 06:11:09 PM PDT 24
Peak memory 239424 kb
Host smart-ee83def4-5f39-441a-9b2e-ca44dfea514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124504817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.124504817
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1844071666
Short name T665
Test name
Test status
Simulation time 461560901 ps
CPU time 2.84 seconds
Started Jun 22 06:11:08 PM PDT 24
Finished Jun 22 06:11:12 PM PDT 24
Peak memory 232900 kb
Host smart-96448c22-48f8-4d94-9f25-6a07bf946c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844071666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1844071666
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.4257649251
Short name T593
Test name
Test status
Simulation time 652561022 ps
CPU time 10.79 seconds
Started Jun 22 06:11:05 PM PDT 24
Finished Jun 22 06:11:16 PM PDT 24
Peak memory 220072 kb
Host smart-bb14280d-c6ce-4b1f-a693-a8bd0c5a2fb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4257649251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.4257649251
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3445023183
Short name T549
Test name
Test status
Simulation time 1075675680 ps
CPU time 13.86 seconds
Started Jun 22 06:11:06 PM PDT 24
Finished Jun 22 06:11:20 PM PDT 24
Peak memory 216432 kb
Host smart-a56c1d0b-361d-40d6-b739-3dac66d59985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445023183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3445023183
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.41273911
Short name T567
Test name
Test status
Simulation time 783041145 ps
CPU time 3.14 seconds
Started Jun 22 06:11:05 PM PDT 24
Finished Jun 22 06:11:09 PM PDT 24
Peak memory 216364 kb
Host smart-933e508c-ead5-48d2-834d-d544a8f0c02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41273911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.41273911
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.629335420
Short name T539
Test name
Test status
Simulation time 106938757 ps
CPU time 1.34 seconds
Started Jun 22 06:11:07 PM PDT 24
Finished Jun 22 06:11:09 PM PDT 24
Peak memory 207592 kb
Host smart-91493cd5-61e8-4d1a-bad5-91db9c07b0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629335420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.629335420
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4111404660
Short name T418
Test name
Test status
Simulation time 70994586 ps
CPU time 0.91 seconds
Started Jun 22 06:11:04 PM PDT 24
Finished Jun 22 06:11:06 PM PDT 24
Peak memory 206104 kb
Host smart-fcab805a-ec26-4681-aab8-afa0f54dec66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111404660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4111404660
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.539433457
Short name T486
Test name
Test status
Simulation time 871701356 ps
CPU time 6.65 seconds
Started Jun 22 06:11:05 PM PDT 24
Finished Jun 22 06:11:12 PM PDT 24
Peak memory 224640 kb
Host smart-4b6df60a-0fe6-481f-86ea-d622f2539467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539433457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.539433457
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2306568579
Short name T527
Test name
Test status
Simulation time 25017099 ps
CPU time 0.73 seconds
Started Jun 22 06:11:13 PM PDT 24
Finished Jun 22 06:11:14 PM PDT 24
Peak memory 204920 kb
Host smart-b0c321d5-066b-42a5-8231-9fb8211fb3a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306568579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2306568579
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3966538665
Short name T820
Test name
Test status
Simulation time 9130608655 ps
CPU time 20.98 seconds
Started Jun 22 06:11:05 PM PDT 24
Finished Jun 22 06:11:27 PM PDT 24
Peak memory 224824 kb
Host smart-ab97a15d-0838-4922-8f9f-343c19fe6305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966538665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3966538665
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3006374064
Short name T415
Test name
Test status
Simulation time 96682161 ps
CPU time 0.76 seconds
Started Jun 22 06:11:09 PM PDT 24
Finished Jun 22 06:11:10 PM PDT 24
Peak memory 205728 kb
Host smart-81afa2a2-1968-49d9-b933-87f5a0360d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006374064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3006374064
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.656021074
Short name T738
Test name
Test status
Simulation time 1400512782 ps
CPU time 4.42 seconds
Started Jun 22 06:11:11 PM PDT 24
Finished Jun 22 06:11:16 PM PDT 24
Peak memory 219732 kb
Host smart-a8d9dc62-b3f4-4e98-93ba-fd6ed10a5987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656021074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.656021074
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.904205786
Short name T209
Test name
Test status
Simulation time 25650570088 ps
CPU time 105.93 seconds
Started Jun 22 06:11:10 PM PDT 24
Finished Jun 22 06:12:56 PM PDT 24
Peak memory 254004 kb
Host smart-83b8312a-f5c1-4460-bb81-4a733c4edbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904205786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.904205786
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3101177961
Short name T10
Test name
Test status
Simulation time 2090934885 ps
CPU time 18.02 seconds
Started Jun 22 06:11:10 PM PDT 24
Finished Jun 22 06:11:29 PM PDT 24
Peak memory 232856 kb
Host smart-05ee1995-8855-45b2-b35b-243d9642cb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101177961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3101177961
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2107344490
Short name T573
Test name
Test status
Simulation time 2593314760 ps
CPU time 28.67 seconds
Started Jun 22 06:11:03 PM PDT 24
Finished Jun 22 06:11:33 PM PDT 24
Peak memory 233012 kb
Host smart-7c0a02a9-7723-4e25-ae4d-28768c1d19e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107344490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2107344490
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3351608364
Short name T398
Test name
Test status
Simulation time 206728810 ps
CPU time 2.52 seconds
Started Jun 22 06:11:03 PM PDT 24
Finished Jun 22 06:11:07 PM PDT 24
Peak memory 232576 kb
Host smart-56712dd4-7ad4-4296-8109-7905ab75b6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351608364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3351608364
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1272964049
Short name T56
Test name
Test status
Simulation time 372482499 ps
CPU time 4.17 seconds
Started Jun 22 06:11:06 PM PDT 24
Finished Jun 22 06:11:11 PM PDT 24
Peak memory 224644 kb
Host smart-8761af99-62ee-4290-8d05-671007fa3f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272964049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1272964049
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1992403990
Short name T858
Test name
Test status
Simulation time 1532231504 ps
CPU time 3.66 seconds
Started Jun 22 06:11:06 PM PDT 24
Finished Jun 22 06:11:10 PM PDT 24
Peak memory 232892 kb
Host smart-a97c3a0d-eacd-4452-b5d4-6ec4ab36e733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992403990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1992403990
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3789180362
Short name T687
Test name
Test status
Simulation time 4147200849 ps
CPU time 12 seconds
Started Jun 22 06:11:12 PM PDT 24
Finished Jun 22 06:11:24 PM PDT 24
Peak memory 220484 kb
Host smart-030d38ca-bf1d-4bc1-8901-700d5d477629
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3789180362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3789180362
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.827925248
Short name T748
Test name
Test status
Simulation time 28116816837 ps
CPU time 105.41 seconds
Started Jun 22 06:11:11 PM PDT 24
Finished Jun 22 06:12:57 PM PDT 24
Peak memory 257656 kb
Host smart-607e8b78-a9a5-4dc1-b9b9-0895c3b1b266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827925248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.827925248
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3646534867
Short name T400
Test name
Test status
Simulation time 4258094327 ps
CPU time 11.91 seconds
Started Jun 22 06:11:04 PM PDT 24
Finished Jun 22 06:11:17 PM PDT 24
Peak memory 216596 kb
Host smart-29ad0248-b52d-43c9-8b43-f69fe8154cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646534867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3646534867
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1453313848
Short name T843
Test name
Test status
Simulation time 553915162 ps
CPU time 2.76 seconds
Started Jun 22 06:11:05 PM PDT 24
Finished Jun 22 06:11:09 PM PDT 24
Peak memory 216392 kb
Host smart-3689d79d-0174-4d3c-b671-fda684fddc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453313848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1453313848
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3662319547
Short name T615
Test name
Test status
Simulation time 673273705 ps
CPU time 1.75 seconds
Started Jun 22 06:11:02 PM PDT 24
Finished Jun 22 06:11:04 PM PDT 24
Peak memory 216444 kb
Host smart-36251cb3-f71e-4027-a7e1-217364c1952f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662319547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3662319547
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.36080595
Short name T596
Test name
Test status
Simulation time 146751332 ps
CPU time 0.91 seconds
Started Jun 22 06:11:04 PM PDT 24
Finished Jun 22 06:11:06 PM PDT 24
Peak memory 206104 kb
Host smart-157a1d8f-d110-4366-ac0c-df948c514e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36080595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.36080595
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.812298676
Short name T248
Test name
Test status
Simulation time 3457191508 ps
CPU time 5.52 seconds
Started Jun 22 06:11:04 PM PDT 24
Finished Jun 22 06:11:10 PM PDT 24
Peak memory 232936 kb
Host smart-787c9235-70f2-4104-88e8-8e71efee2c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812298676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.812298676
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.922068875
Short name T728
Test name
Test status
Simulation time 35333038 ps
CPU time 0.73 seconds
Started Jun 22 06:11:09 PM PDT 24
Finished Jun 22 06:11:10 PM PDT 24
Peak memory 205492 kb
Host smart-8893513c-29f9-4a7a-ae34-c9fcf6e236b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922068875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.922068875
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.329039017
Short name T518
Test name
Test status
Simulation time 136172519 ps
CPU time 4.07 seconds
Started Jun 22 06:11:12 PM PDT 24
Finished Jun 22 06:11:17 PM PDT 24
Peak memory 232860 kb
Host smart-ad04bc50-4be0-461e-a81a-3449ff2265d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329039017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.329039017
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1135483317
Short name T744
Test name
Test status
Simulation time 42404171 ps
CPU time 0.79 seconds
Started Jun 22 06:11:09 PM PDT 24
Finished Jun 22 06:11:10 PM PDT 24
Peak memory 205972 kb
Host smart-b2636d72-3f2b-46e7-af15-cdda3dbf137e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135483317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1135483317
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3777778397
Short name T917
Test name
Test status
Simulation time 14410869508 ps
CPU time 70.78 seconds
Started Jun 22 06:11:14 PM PDT 24
Finished Jun 22 06:12:25 PM PDT 24
Peak memory 241236 kb
Host smart-ff96d3bb-c26a-454f-afbb-6bdf5b5ba1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777778397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3777778397
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3370670503
Short name T285
Test name
Test status
Simulation time 33233385082 ps
CPU time 151.21 seconds
Started Jun 22 06:11:09 PM PDT 24
Finished Jun 22 06:13:41 PM PDT 24
Peak memory 252312 kb
Host smart-6a0513c7-7c9c-45ea-82a5-31b8b21fa065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370670503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3370670503
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.652239960
Short name T569
Test name
Test status
Simulation time 201752544 ps
CPU time 3.42 seconds
Started Jun 22 06:11:10 PM PDT 24
Finished Jun 22 06:11:14 PM PDT 24
Peak memory 224644 kb
Host smart-c2755496-2798-4bc8-9417-3b548b0d5c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652239960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.652239960
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3008888755
Short name T796
Test name
Test status
Simulation time 112499974 ps
CPU time 2 seconds
Started Jun 22 06:11:11 PM PDT 24
Finished Jun 22 06:11:14 PM PDT 24
Peak memory 223016 kb
Host smart-8c53ebd2-648a-4d27-afa0-2ea6fd578a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008888755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3008888755
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1921005429
Short name T812
Test name
Test status
Simulation time 57194445 ps
CPU time 2.74 seconds
Started Jun 22 06:11:11 PM PDT 24
Finished Jun 22 06:11:14 PM PDT 24
Peak memory 232572 kb
Host smart-090f3b9c-a7db-4f10-a261-1aedc8c8925b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921005429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1921005429
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3878490083
Short name T720
Test name
Test status
Simulation time 7030388170 ps
CPU time 12.55 seconds
Started Jun 22 06:11:11 PM PDT 24
Finished Jun 22 06:11:24 PM PDT 24
Peak memory 232972 kb
Host smart-80619133-82ce-4059-8905-46d6f0658552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878490083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3878490083
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2961326261
Short name T607
Test name
Test status
Simulation time 1207077906 ps
CPU time 6.03 seconds
Started Jun 22 06:11:13 PM PDT 24
Finished Jun 22 06:11:19 PM PDT 24
Peak memory 224652 kb
Host smart-4355f9dc-4b07-4d6e-88a7-e22738543167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961326261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2961326261
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.969630076
Short name T49
Test name
Test status
Simulation time 328293663 ps
CPU time 3.2 seconds
Started Jun 22 06:11:09 PM PDT 24
Finished Jun 22 06:11:13 PM PDT 24
Peak memory 220708 kb
Host smart-41881538-ee00-4315-8fb0-b6c9433a675a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=969630076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.969630076
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3705377021
Short name T165
Test name
Test status
Simulation time 11953536778 ps
CPU time 156.61 seconds
Started Jun 22 06:11:11 PM PDT 24
Finished Jun 22 06:13:48 PM PDT 24
Peak memory 251972 kb
Host smart-f6b3b763-9f09-4334-9fe4-82ddcbae6e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705377021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3705377021
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2684464806
Short name T500
Test name
Test status
Simulation time 12459029 ps
CPU time 0.76 seconds
Started Jun 22 06:11:10 PM PDT 24
Finished Jun 22 06:11:11 PM PDT 24
Peak memory 205816 kb
Host smart-1e3e8ac6-a3f8-4723-b03c-5dd5f6c4ad29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684464806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2684464806
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1698966825
Short name T537
Test name
Test status
Simulation time 2115912636 ps
CPU time 4.86 seconds
Started Jun 22 06:11:09 PM PDT 24
Finished Jun 22 06:11:14 PM PDT 24
Peak memory 216436 kb
Host smart-0aec8d26-178a-4982-8d2f-2a3029d033cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698966825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1698966825
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.574464022
Short name T876
Test name
Test status
Simulation time 177223415 ps
CPU time 3.04 seconds
Started Jun 22 06:11:08 PM PDT 24
Finished Jun 22 06:11:11 PM PDT 24
Peak memory 216396 kb
Host smart-07efb7a7-0931-4ce6-900a-312cea1a2f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574464022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.574464022
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3585396308
Short name T884
Test name
Test status
Simulation time 39477668 ps
CPU time 0.84 seconds
Started Jun 22 06:11:08 PM PDT 24
Finished Jun 22 06:11:09 PM PDT 24
Peak memory 206096 kb
Host smart-9c296f39-be7c-446b-acf5-08d8a613d56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585396308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3585396308
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.4116096733
Short name T423
Test name
Test status
Simulation time 1443563034 ps
CPU time 6.03 seconds
Started Jun 22 06:11:10 PM PDT 24
Finished Jun 22 06:11:16 PM PDT 24
Peak memory 224664 kb
Host smart-d34d3402-b123-4e12-b805-82a08a8f11d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116096733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.4116096733
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1786090039
Short name T516
Test name
Test status
Simulation time 12040024 ps
CPU time 0.76 seconds
Started Jun 22 06:09:40 PM PDT 24
Finished Jun 22 06:09:41 PM PDT 24
Peak memory 205508 kb
Host smart-fe444fa5-9583-4244-a91f-05ed4057ed14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786090039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
786090039
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.404534087
Short name T251
Test name
Test status
Simulation time 248564548 ps
CPU time 4.41 seconds
Started Jun 22 06:09:35 PM PDT 24
Finished Jun 22 06:09:40 PM PDT 24
Peak memory 224628 kb
Host smart-2b35654b-65c7-4a4f-a171-50a25e864e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404534087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.404534087
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2607240155
Short name T170
Test name
Test status
Simulation time 37943334 ps
CPU time 0.79 seconds
Started Jun 22 06:09:33 PM PDT 24
Finished Jun 22 06:09:34 PM PDT 24
Peak memory 206756 kb
Host smart-044263db-c79b-4562-8dce-c2fe4ef29fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607240155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2607240155
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.249974455
Short name T562
Test name
Test status
Simulation time 4110752043 ps
CPU time 32.64 seconds
Started Jun 22 06:09:36 PM PDT 24
Finished Jun 22 06:10:10 PM PDT 24
Peak memory 241188 kb
Host smart-35006c85-5d98-481e-a3e2-918aa922cece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249974455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.249974455
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1787339325
Short name T334
Test name
Test status
Simulation time 52684033319 ps
CPU time 89.54 seconds
Started Jun 22 06:09:40 PM PDT 24
Finished Jun 22 06:11:10 PM PDT 24
Peak memory 249660 kb
Host smart-b3650e68-3958-4d7e-ab88-ad2c3786e662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787339325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1787339325
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.889401226
Short name T958
Test name
Test status
Simulation time 5782956050 ps
CPU time 18.46 seconds
Started Jun 22 06:09:36 PM PDT 24
Finished Jun 22 06:09:56 PM PDT 24
Peak memory 232848 kb
Host smart-1c249f2f-f167-4925-b9b2-13360d9fa306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889401226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.889401226
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3126392819
Short name T370
Test name
Test status
Simulation time 34103871 ps
CPU time 2.6 seconds
Started Jun 22 06:09:45 PM PDT 24
Finished Jun 22 06:09:48 PM PDT 24
Peak memory 226760 kb
Host smart-977a3825-f0eb-4a88-9ad0-ff6e6d070f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126392819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3126392819
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1995273950
Short name T963
Test name
Test status
Simulation time 2720453858 ps
CPU time 16.67 seconds
Started Jun 22 06:09:39 PM PDT 24
Finished Jun 22 06:09:56 PM PDT 24
Peak memory 233996 kb
Host smart-8961bba4-3738-40d2-a161-75a2250d8e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995273950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1995273950
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3401046188
Short name T678
Test name
Test status
Simulation time 321633911 ps
CPU time 4.5 seconds
Started Jun 22 06:09:35 PM PDT 24
Finished Jun 22 06:09:40 PM PDT 24
Peak memory 224624 kb
Host smart-fff826b6-d286-450f-919e-4fe89fbc8c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401046188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3401046188
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1245284137
Short name T614
Test name
Test status
Simulation time 8238652303 ps
CPU time 8.74 seconds
Started Jun 22 06:09:37 PM PDT 24
Finished Jun 22 06:09:47 PM PDT 24
Peak memory 232980 kb
Host smart-1afa81cf-835a-48a8-9c5a-0038f96e5c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245284137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1245284137
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2368128104
Short name T656
Test name
Test status
Simulation time 678458208 ps
CPU time 5.67 seconds
Started Jun 22 06:09:37 PM PDT 24
Finished Jun 22 06:09:44 PM PDT 24
Peak memory 220056 kb
Host smart-4fe31f97-1e53-4e68-b62f-eca5c69024fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2368128104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2368128104
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3603817492
Short name T82
Test name
Test status
Simulation time 79816017 ps
CPU time 0.97 seconds
Started Jun 22 06:09:36 PM PDT 24
Finished Jun 22 06:09:37 PM PDT 24
Peak memory 235504 kb
Host smart-dca801cb-21bc-49b8-b9cb-0089c6e258f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603817492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3603817492
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1443866131
Short name T19
Test name
Test status
Simulation time 119150803 ps
CPU time 1.07 seconds
Started Jun 22 06:09:46 PM PDT 24
Finished Jun 22 06:09:48 PM PDT 24
Peak memory 206800 kb
Host smart-e97a468e-07c5-4f38-9222-57b68ec22f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443866131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1443866131
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1237421571
Short name T888
Test name
Test status
Simulation time 56989716 ps
CPU time 0.71 seconds
Started Jun 22 06:09:27 PM PDT 24
Finished Jun 22 06:09:28 PM PDT 24
Peak memory 205820 kb
Host smart-26545f8b-fa8a-4c61-bf07-f837cb5d0157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237421571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1237421571
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.636244898
Short name T437
Test name
Test status
Simulation time 37407562976 ps
CPU time 9.38 seconds
Started Jun 22 06:09:34 PM PDT 24
Finished Jun 22 06:09:44 PM PDT 24
Peak memory 216528 kb
Host smart-d6f7898a-861e-4362-984c-ad9584c28e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636244898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.636244898
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1676478672
Short name T392
Test name
Test status
Simulation time 93550256 ps
CPU time 1.33 seconds
Started Jun 22 06:09:36 PM PDT 24
Finished Jun 22 06:09:39 PM PDT 24
Peak memory 216644 kb
Host smart-da1858ed-929d-4050-b8d9-74b5c9fac82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676478672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1676478672
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3355356365
Short name T376
Test name
Test status
Simulation time 140019746 ps
CPU time 0.96 seconds
Started Jun 22 06:09:38 PM PDT 24
Finished Jun 22 06:09:39 PM PDT 24
Peak memory 206088 kb
Host smart-c669479b-5a76-43c8-bbf2-6ce3a500fc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355356365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3355356365
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.55338932
Short name T783
Test name
Test status
Simulation time 812672377 ps
CPU time 3.71 seconds
Started Jun 22 06:09:38 PM PDT 24
Finished Jun 22 06:09:42 PM PDT 24
Peak memory 224636 kb
Host smart-c8df5590-7f24-424c-946f-a279273b49d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55338932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.55338932
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.709996340
Short name T802
Test name
Test status
Simulation time 54543314 ps
CPU time 0.69 seconds
Started Jun 22 06:11:19 PM PDT 24
Finished Jun 22 06:11:21 PM PDT 24
Peak memory 205536 kb
Host smart-c7760e5e-a899-455e-850c-ff3a9cbeaa40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709996340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.709996340
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3834950908
Short name T759
Test name
Test status
Simulation time 160462974 ps
CPU time 3.47 seconds
Started Jun 22 06:11:17 PM PDT 24
Finished Jun 22 06:11:21 PM PDT 24
Peak memory 224700 kb
Host smart-f00be2eb-b9e6-4306-966d-175325caec45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834950908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3834950908
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3506028658
Short name T727
Test name
Test status
Simulation time 38348299 ps
CPU time 0.75 seconds
Started Jun 22 06:11:07 PM PDT 24
Finished Jun 22 06:11:08 PM PDT 24
Peak memory 207064 kb
Host smart-22744d27-71f7-492c-beef-4f54a47d942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506028658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3506028658
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3208898762
Short name T225
Test name
Test status
Simulation time 1100908482 ps
CPU time 14.73 seconds
Started Jun 22 06:11:23 PM PDT 24
Finished Jun 22 06:11:39 PM PDT 24
Peak memory 239148 kb
Host smart-b273b1f3-24b6-40d1-a534-691e89a1d78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208898762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3208898762
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2675165005
Short name T671
Test name
Test status
Simulation time 7593465883 ps
CPU time 35.87 seconds
Started Jun 22 06:11:22 PM PDT 24
Finished Jun 22 06:11:59 PM PDT 24
Peak memory 237852 kb
Host smart-141bcb16-e900-443b-98a8-016a5ef1fb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675165005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2675165005
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2114955044
Short name T295
Test name
Test status
Simulation time 6184035052 ps
CPU time 76.74 seconds
Started Jun 22 06:11:17 PM PDT 24
Finished Jun 22 06:12:34 PM PDT 24
Peak memory 249316 kb
Host smart-d809618c-9fce-423a-b38f-f961d1f1c06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114955044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2114955044
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1261428256
Short name T623
Test name
Test status
Simulation time 286458595 ps
CPU time 7.6 seconds
Started Jun 22 06:11:18 PM PDT 24
Finished Jun 22 06:11:26 PM PDT 24
Peak memory 234312 kb
Host smart-e80a800f-1dd8-45b9-a847-39a3404023de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261428256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1261428256
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.764002494
Short name T800
Test name
Test status
Simulation time 321083025 ps
CPU time 3.27 seconds
Started Jun 22 06:11:18 PM PDT 24
Finished Jun 22 06:11:22 PM PDT 24
Peak memory 224644 kb
Host smart-62c89a6b-f392-4358-9c86-551d34ca38b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764002494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.764002494
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1997776874
Short name T50
Test name
Test status
Simulation time 10533474938 ps
CPU time 25.5 seconds
Started Jun 22 06:11:19 PM PDT 24
Finished Jun 22 06:11:45 PM PDT 24
Peak memory 234400 kb
Host smart-b43b4b6a-9d85-4782-9ccf-5145aa9daa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997776874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1997776874
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1762537372
Short name T784
Test name
Test status
Simulation time 546057398 ps
CPU time 7.62 seconds
Started Jun 22 06:11:22 PM PDT 24
Finished Jun 22 06:11:30 PM PDT 24
Peak memory 232848 kb
Host smart-dd95df3c-9f4a-4edd-9321-92fa24b96430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762537372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1762537372
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1517925075
Short name T782
Test name
Test status
Simulation time 698959692 ps
CPU time 3.85 seconds
Started Jun 22 06:11:15 PM PDT 24
Finished Jun 22 06:11:19 PM PDT 24
Peak memory 232896 kb
Host smart-bc0cf4cd-854b-41db-ab7a-9ca8fec4a8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517925075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1517925075
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2602252113
Short name T875
Test name
Test status
Simulation time 1104147054 ps
CPU time 11.44 seconds
Started Jun 22 06:11:17 PM PDT 24
Finished Jun 22 06:11:29 PM PDT 24
Peak memory 222812 kb
Host smart-6d278eac-c428-4023-97a1-608341d1c51a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2602252113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2602252113
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2055021077
Short name T204
Test name
Test status
Simulation time 22235463469 ps
CPU time 176.78 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:14:23 PM PDT 24
Peak memory 272632 kb
Host smart-150b9fc6-7f25-4c11-9548-7f0cab8e60be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055021077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2055021077
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1219821022
Short name T496
Test name
Test status
Simulation time 7792880279 ps
CPU time 34.66 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:12:01 PM PDT 24
Peak memory 216620 kb
Host smart-6bfd0b7e-162f-4e64-8792-ffc2c9250d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219821022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1219821022
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2322834246
Short name T31
Test name
Test status
Simulation time 631875310 ps
CPU time 1.25 seconds
Started Jun 22 06:11:12 PM PDT 24
Finished Jun 22 06:11:14 PM PDT 24
Peak memory 208076 kb
Host smart-ed4c73c1-9f7f-467b-8aa8-a726b8659d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322834246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2322834246
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3832033821
Short name T586
Test name
Test status
Simulation time 140015228 ps
CPU time 1.66 seconds
Started Jun 22 06:11:26 PM PDT 24
Finished Jun 22 06:11:29 PM PDT 24
Peak memory 216384 kb
Host smart-6221b3da-5ea3-470a-acfb-3d2247f94f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832033821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3832033821
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.958030570
Short name T881
Test name
Test status
Simulation time 528157431 ps
CPU time 0.89 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:11:27 PM PDT 24
Peak memory 207128 kb
Host smart-b5707494-0104-4b61-9426-177ead63600b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958030570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.958030570
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.4089241542
Short name T481
Test name
Test status
Simulation time 41647971526 ps
CPU time 13.47 seconds
Started Jun 22 06:11:19 PM PDT 24
Finished Jun 22 06:11:33 PM PDT 24
Peak memory 224820 kb
Host smart-3eecca0b-758e-489a-814a-2a0722d3f31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089241542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.4089241542
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2392723204
Short name T356
Test name
Test status
Simulation time 30861717 ps
CPU time 0.76 seconds
Started Jun 22 06:11:25 PM PDT 24
Finished Jun 22 06:11:28 PM PDT 24
Peak memory 204936 kb
Host smart-18bc056d-bc8a-478a-9f80-fb5ea36be3f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392723204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2392723204
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4038691749
Short name T618
Test name
Test status
Simulation time 164287519 ps
CPU time 3.97 seconds
Started Jun 22 06:11:16 PM PDT 24
Finished Jun 22 06:11:20 PM PDT 24
Peak memory 232860 kb
Host smart-19837195-80a7-458c-8397-140a458dd1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038691749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4038691749
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1927620627
Short name T472
Test name
Test status
Simulation time 56570380 ps
CPU time 0.79 seconds
Started Jun 22 06:11:16 PM PDT 24
Finished Jun 22 06:11:17 PM PDT 24
Peak memory 205636 kb
Host smart-c8b54780-a359-4997-94fb-c9159c1abb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927620627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1927620627
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2471062424
Short name T175
Test name
Test status
Simulation time 29385929976 ps
CPU time 72.73 seconds
Started Jun 22 06:11:15 PM PDT 24
Finished Jun 22 06:12:28 PM PDT 24
Peak memory 240668 kb
Host smart-9a3ae5c9-fc4f-4d2a-8f34-9d247adcec03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471062424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2471062424
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1382777084
Short name T563
Test name
Test status
Simulation time 29648117451 ps
CPU time 269.71 seconds
Started Jun 22 06:11:23 PM PDT 24
Finished Jun 22 06:15:54 PM PDT 24
Peak memory 241208 kb
Host smart-0bf99d05-6be2-4b19-a669-cd29982181a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382777084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1382777084
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1715472754
Short name T424
Test name
Test status
Simulation time 3581812486 ps
CPU time 16.88 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:11:42 PM PDT 24
Peak memory 235112 kb
Host smart-3a5363f5-dd4b-4e5d-8636-b45766674c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715472754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1715472754
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3967673164
Short name T594
Test name
Test status
Simulation time 1019709426 ps
CPU time 6.61 seconds
Started Jun 22 06:11:25 PM PDT 24
Finished Jun 22 06:11:34 PM PDT 24
Peak memory 224640 kb
Host smart-a9053c75-5962-4e29-862e-9e0f7d869892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967673164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3967673164
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2607587198
Short name T659
Test name
Test status
Simulation time 11073008217 ps
CPU time 88.22 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:12:54 PM PDT 24
Peak memory 233004 kb
Host smart-58bf1c32-7e70-416a-b2b0-2a7e77195e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607587198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2607587198
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1418873232
Short name T291
Test name
Test status
Simulation time 150038756764 ps
CPU time 28.72 seconds
Started Jun 22 06:11:18 PM PDT 24
Finished Jun 22 06:11:47 PM PDT 24
Peak memory 240928 kb
Host smart-bdb28dd5-ca05-4588-ac66-ea1437a17e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418873232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1418873232
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2013232465
Short name T895
Test name
Test status
Simulation time 45333366905 ps
CPU time 21.06 seconds
Started Jun 22 06:11:23 PM PDT 24
Finished Jun 22 06:11:45 PM PDT 24
Peak memory 241256 kb
Host smart-c57c4db0-73b1-4d5b-9254-7ac13f40a93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013232465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2013232465
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4099471118
Short name T513
Test name
Test status
Simulation time 5131762608 ps
CPU time 12.62 seconds
Started Jun 22 06:11:23 PM PDT 24
Finished Jun 22 06:11:37 PM PDT 24
Peak memory 223324 kb
Host smart-36e04ef2-867f-402e-b86a-815fe40e0cbb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4099471118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4099471118
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3671654033
Short name T145
Test name
Test status
Simulation time 48107596550 ps
CPU time 409.28 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:18:15 PM PDT 24
Peak memory 253220 kb
Host smart-fe687335-a910-4679-a6d9-48b72ccf679c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671654033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3671654033
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.488505747
Short name T458
Test name
Test status
Simulation time 3156645492 ps
CPU time 24.13 seconds
Started Jun 22 06:11:17 PM PDT 24
Finished Jun 22 06:11:42 PM PDT 24
Peak memory 220640 kb
Host smart-54b16979-a4b0-4975-901c-07b58785c87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488505747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.488505747
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2390111607
Short name T571
Test name
Test status
Simulation time 11702365523 ps
CPU time 4.93 seconds
Started Jun 22 06:11:22 PM PDT 24
Finished Jun 22 06:11:28 PM PDT 24
Peak memory 216548 kb
Host smart-6cc5d72e-c078-4bde-81ce-2e8ae7c1e1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390111607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2390111607
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3503507712
Short name T582
Test name
Test status
Simulation time 104370673 ps
CPU time 1.72 seconds
Started Jun 22 06:11:22 PM PDT 24
Finished Jun 22 06:11:24 PM PDT 24
Peak memory 208208 kb
Host smart-d2fcc7f8-76f9-4735-9e70-7d596b290132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503507712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3503507712
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2211718180
Short name T556
Test name
Test status
Simulation time 72101500 ps
CPU time 0.95 seconds
Started Jun 22 06:11:16 PM PDT 24
Finished Jun 22 06:11:17 PM PDT 24
Peak memory 206048 kb
Host smart-b22cff53-bc68-4359-a13d-e35be720fb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211718180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2211718180
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3619318092
Short name T43
Test name
Test status
Simulation time 3801524837 ps
CPU time 12.39 seconds
Started Jun 22 06:11:22 PM PDT 24
Finished Jun 22 06:11:35 PM PDT 24
Peak memory 239168 kb
Host smart-8e803ecc-7bd2-4c41-a338-329c64bd8762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619318092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3619318092
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.4052935775
Short name T470
Test name
Test status
Simulation time 15380928 ps
CPU time 0.7 seconds
Started Jun 22 06:11:22 PM PDT 24
Finished Jun 22 06:11:24 PM PDT 24
Peak memory 204916 kb
Host smart-70b6d622-35ae-4c13-9e31-7a08dcad3216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052935775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
4052935775
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2791771736
Short name T854
Test name
Test status
Simulation time 387789130 ps
CPU time 2.73 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:11:29 PM PDT 24
Peak memory 232884 kb
Host smart-dd588251-4b7b-4396-9a20-47dd349cc905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791771736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2791771736
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1272077074
Short name T507
Test name
Test status
Simulation time 22928112 ps
CPU time 0.82 seconds
Started Jun 22 06:11:25 PM PDT 24
Finished Jun 22 06:11:27 PM PDT 24
Peak memory 206752 kb
Host smart-17b325ae-3c6f-4392-a6f0-890f261abc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272077074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1272077074
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2984245764
Short name T463
Test name
Test status
Simulation time 136575136 ps
CPU time 4.26 seconds
Started Jun 22 06:11:22 PM PDT 24
Finished Jun 22 06:11:28 PM PDT 24
Peak memory 236220 kb
Host smart-efd6870a-8787-44c8-af60-564713a6d9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984245764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2984245764
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2250267347
Short name T822
Test name
Test status
Simulation time 196408656928 ps
CPU time 507.28 seconds
Started Jun 22 06:11:22 PM PDT 24
Finished Jun 22 06:19:50 PM PDT 24
Peak memory 272008 kb
Host smart-15ec1e7a-e60d-4b98-8e8c-dffc8a7aadca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250267347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2250267347
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.193500140
Short name T147
Test name
Test status
Simulation time 7243991711 ps
CPU time 47.07 seconds
Started Jun 22 06:11:25 PM PDT 24
Finished Jun 22 06:12:14 PM PDT 24
Peak memory 249164 kb
Host smart-b5e01296-dbe9-4018-a71b-3149f3298208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193500140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.193500140
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2587048359
Short name T314
Test name
Test status
Simulation time 579085985 ps
CPU time 15.72 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:11:41 PM PDT 24
Peak memory 240832 kb
Host smart-5d502d03-bcf4-464d-80f9-6c7c589d4d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587048359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2587048359
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.584417822
Short name T551
Test name
Test status
Simulation time 2551307400 ps
CPU time 6.91 seconds
Started Jun 22 06:11:25 PM PDT 24
Finished Jun 22 06:11:33 PM PDT 24
Peak memory 224764 kb
Host smart-7b17291c-cf63-477e-b4f3-6d0087ca21b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584417822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.584417822
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2499938574
Short name T223
Test name
Test status
Simulation time 3536117191 ps
CPU time 10.57 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:11:36 PM PDT 24
Peak memory 233024 kb
Host smart-c83c7418-19ca-4269-a616-b71638fc45f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499938574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2499938574
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3477253827
Short name T821
Test name
Test status
Simulation time 4066430081 ps
CPU time 10.15 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:11:36 PM PDT 24
Peak memory 224612 kb
Host smart-adda212a-1aa4-4353-ab8e-7be248091d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477253827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3477253827
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4056958214
Short name T469
Test name
Test status
Simulation time 1853740481 ps
CPU time 6.77 seconds
Started Jun 22 06:11:21 PM PDT 24
Finished Jun 22 06:11:28 PM PDT 24
Peak memory 232824 kb
Host smart-91d8068a-1376-412b-81cd-27c0054f0a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056958214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4056958214
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3022368384
Short name T152
Test name
Test status
Simulation time 146259927 ps
CPU time 3.76 seconds
Started Jun 22 06:11:25 PM PDT 24
Finished Jun 22 06:11:30 PM PDT 24
Peak memory 220176 kb
Host smart-f8312d39-164d-4834-b66c-72c2f141b7f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3022368384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3022368384
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2483659072
Short name T14
Test name
Test status
Simulation time 22827013926 ps
CPU time 132.11 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:13:37 PM PDT 24
Peak memory 249912 kb
Host smart-402fd47a-b284-49a5-907e-760fc668da4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483659072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2483659072
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.129157308
Short name T322
Test name
Test status
Simulation time 1273508693 ps
CPU time 12.94 seconds
Started Jun 22 06:11:25 PM PDT 24
Finished Jun 22 06:11:40 PM PDT 24
Peak memory 216472 kb
Host smart-cb106c92-b390-4e20-acf8-2734f3fb32f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129157308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.129157308
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2473745726
Short name T484
Test name
Test status
Simulation time 1557496313 ps
CPU time 5.63 seconds
Started Jun 22 06:11:22 PM PDT 24
Finished Jun 22 06:11:29 PM PDT 24
Peak memory 216420 kb
Host smart-9dba740a-0120-4d00-bb1d-ccbb10a02a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473745726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2473745726
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1272458616
Short name T757
Test name
Test status
Simulation time 16668242 ps
CPU time 0.84 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:11:27 PM PDT 24
Peak memory 207144 kb
Host smart-0b2a0730-124a-4f30-a690-338b9d1616e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272458616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1272458616
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2254309511
Short name T850
Test name
Test status
Simulation time 16093806 ps
CPU time 0.77 seconds
Started Jun 22 06:11:25 PM PDT 24
Finished Jun 22 06:11:28 PM PDT 24
Peak memory 206104 kb
Host smart-062e1db9-3902-4a69-995b-a9ee9608f2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254309511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2254309511
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3879663655
Short name T552
Test name
Test status
Simulation time 1266229318 ps
CPU time 5.23 seconds
Started Jun 22 06:11:23 PM PDT 24
Finished Jun 22 06:11:29 PM PDT 24
Peak memory 224692 kb
Host smart-ecb01b97-e222-43a8-8549-945857a1b134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879663655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3879663655
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2539569072
Short name T508
Test name
Test status
Simulation time 12692229 ps
CPU time 0.73 seconds
Started Jun 22 06:11:33 PM PDT 24
Finished Jun 22 06:11:34 PM PDT 24
Peak memory 205748 kb
Host smart-95802c9d-1014-423e-95fa-526a7c4ad527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539569072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2539569072
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.938111571
Short name T598
Test name
Test status
Simulation time 1670596124 ps
CPU time 13.92 seconds
Started Jun 22 06:11:25 PM PDT 24
Finished Jun 22 06:11:41 PM PDT 24
Peak memory 232812 kb
Host smart-db4e9bb2-bca0-4aa1-8283-c40913e48134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938111571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.938111571
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3337641229
Short name T460
Test name
Test status
Simulation time 14500864 ps
CPU time 0.77 seconds
Started Jun 22 06:11:23 PM PDT 24
Finished Jun 22 06:11:25 PM PDT 24
Peak memory 206728 kb
Host smart-9ebf635a-b8d4-47f8-bcb8-b8a53bebb2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337641229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3337641229
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.950180749
Short name T764
Test name
Test status
Simulation time 131709100 ps
CPU time 0.91 seconds
Started Jun 22 06:11:22 PM PDT 24
Finished Jun 22 06:11:23 PM PDT 24
Peak memory 216112 kb
Host smart-7324c19d-ec06-4af1-ae7e-f73424205b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950180749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.950180749
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3519371042
Short name T406
Test name
Test status
Simulation time 2579350759 ps
CPU time 4.04 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:11:30 PM PDT 24
Peak memory 217672 kb
Host smart-7fe1eae1-0eb5-4422-bece-e7b73585a1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519371042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3519371042
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1917347882
Short name T200
Test name
Test status
Simulation time 582641151881 ps
CPU time 808.71 seconds
Started Jun 22 06:11:25 PM PDT 24
Finished Jun 22 06:24:56 PM PDT 24
Peak memory 265748 kb
Host smart-c5637d16-d418-43b0-a0a1-d8dcafd39e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917347882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1917347882
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1917647384
Short name T95
Test name
Test status
Simulation time 107646284 ps
CPU time 5.35 seconds
Started Jun 22 06:11:22 PM PDT 24
Finished Jun 22 06:11:29 PM PDT 24
Peak memory 232892 kb
Host smart-e9b87419-3ad3-49e3-b3e0-79f7ad87c106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917647384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1917647384
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2736013702
Short name T228
Test name
Test status
Simulation time 697114030 ps
CPU time 3.7 seconds
Started Jun 22 06:11:25 PM PDT 24
Finished Jun 22 06:11:31 PM PDT 24
Peak memory 224624 kb
Host smart-aab6848e-52e8-493f-9528-44f3c0da58e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736013702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2736013702
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2435317342
Short name T899
Test name
Test status
Simulation time 4340364488 ps
CPU time 16.04 seconds
Started Jun 22 06:11:25 PM PDT 24
Finished Jun 22 06:11:43 PM PDT 24
Peak memory 249412 kb
Host smart-1834d81b-5358-4655-b12a-a01c39712c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435317342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2435317342
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1606962016
Short name T638
Test name
Test status
Simulation time 870742472 ps
CPU time 4.48 seconds
Started Jun 22 06:11:27 PM PDT 24
Finished Jun 22 06:11:32 PM PDT 24
Peak memory 232844 kb
Host smart-481ddbe9-a002-4f64-aefb-2c2c4be21e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606962016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1606962016
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.132205816
Short name T705
Test name
Test status
Simulation time 823880575 ps
CPU time 5.36 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:11:32 PM PDT 24
Peak memory 232892 kb
Host smart-3fe2ca4a-db60-4199-97a6-4a77a80f4683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132205816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.132205816
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2769584355
Short name T883
Test name
Test status
Simulation time 773970709 ps
CPU time 5.28 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:11:31 PM PDT 24
Peak memory 222824 kb
Host smart-f6dc5aff-a503-4ec3-88a2-69f6fef601aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2769584355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2769584355
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.996455745
Short name T864
Test name
Test status
Simulation time 236525737 ps
CPU time 1.15 seconds
Started Jun 22 06:11:25 PM PDT 24
Finished Jun 22 06:11:28 PM PDT 24
Peak memory 207212 kb
Host smart-1812afbc-a38b-4f3a-8080-c2690fa5d835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996455745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.996455745
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2368562625
Short name T524
Test name
Test status
Simulation time 329745353 ps
CPU time 5.37 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:11:31 PM PDT 24
Peak memory 219600 kb
Host smart-1c990bce-60fe-4237-ac87-54aa7fe2486a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368562625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2368562625
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2177984668
Short name T33
Test name
Test status
Simulation time 2472432918 ps
CPU time 7.66 seconds
Started Jun 22 06:11:23 PM PDT 24
Finished Jun 22 06:11:32 PM PDT 24
Peak memory 216516 kb
Host smart-d57461eb-7cb6-4bb9-88b7-96650dfdaa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177984668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2177984668
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1750886301
Short name T847
Test name
Test status
Simulation time 1064866010 ps
CPU time 4.15 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:11:29 PM PDT 24
Peak memory 216416 kb
Host smart-221e9efe-a1fc-4e1d-954d-7de53e81da7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750886301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1750886301
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.506055013
Short name T350
Test name
Test status
Simulation time 31418619 ps
CPU time 0.85 seconds
Started Jun 22 06:11:24 PM PDT 24
Finished Jun 22 06:11:26 PM PDT 24
Peak memory 206084 kb
Host smart-4a88644b-0b77-45c2-8941-e0378b76a550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506055013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.506055013
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3404801554
Short name T278
Test name
Test status
Simulation time 3034532092 ps
CPU time 5.81 seconds
Started Jun 22 06:11:22 PM PDT 24
Finished Jun 22 06:11:28 PM PDT 24
Peak memory 232968 kb
Host smart-64390d73-f328-4535-b1e9-c4696fccd6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404801554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3404801554
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3673954297
Short name T840
Test name
Test status
Simulation time 10796296 ps
CPU time 0.7 seconds
Started Jun 22 06:11:28 PM PDT 24
Finished Jun 22 06:11:29 PM PDT 24
Peak memory 205496 kb
Host smart-d34d3665-a362-4786-95c7-eb2f56430391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673954297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3673954297
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1622499211
Short name T896
Test name
Test status
Simulation time 928117115 ps
CPU time 3.22 seconds
Started Jun 22 06:11:31 PM PDT 24
Finished Jun 22 06:11:34 PM PDT 24
Peak memory 224644 kb
Host smart-71e8ccc1-f84c-4510-90c5-28e3de99f005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622499211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1622499211
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.342005387
Short name T643
Test name
Test status
Simulation time 41327848 ps
CPU time 0.82 seconds
Started Jun 22 06:11:30 PM PDT 24
Finished Jun 22 06:11:32 PM PDT 24
Peak memory 206684 kb
Host smart-c1a16278-c20e-4dc7-b4b9-504f5007cb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342005387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.342005387
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1624956725
Short name T208
Test name
Test status
Simulation time 7230545421 ps
CPU time 37.74 seconds
Started Jun 22 06:11:30 PM PDT 24
Finished Jun 22 06:12:08 PM PDT 24
Peak memory 254284 kb
Host smart-e715e3e9-5a2e-4d49-8f42-9cf4e6264168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624956725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1624956725
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.346194722
Short name T86
Test name
Test status
Simulation time 17977734056 ps
CPU time 82.47 seconds
Started Jun 22 06:11:30 PM PDT 24
Finished Jun 22 06:12:53 PM PDT 24
Peak memory 252932 kb
Host smart-99e5e9d0-894a-4844-91d9-393ee8fff983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346194722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.346194722
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3064737907
Short name T176
Test name
Test status
Simulation time 26864646838 ps
CPU time 37.01 seconds
Started Jun 22 06:11:29 PM PDT 24
Finished Jun 22 06:12:07 PM PDT 24
Peak memory 249440 kb
Host smart-f82c3197-a396-4aeb-9400-94534b9d252c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064737907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3064737907
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3637831308
Short name T315
Test name
Test status
Simulation time 1848158258 ps
CPU time 28.38 seconds
Started Jun 22 06:11:31 PM PDT 24
Finished Jun 22 06:12:00 PM PDT 24
Peak memory 241032 kb
Host smart-e4ee6c36-1930-42cb-af7b-857922520863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637831308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3637831308
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.444587090
Short name T779
Test name
Test status
Simulation time 156368990 ps
CPU time 4.97 seconds
Started Jun 22 06:11:30 PM PDT 24
Finished Jun 22 06:11:35 PM PDT 24
Peak memory 232852 kb
Host smart-4e95a73a-7913-4aca-b460-bfb3e86b7351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444587090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.444587090
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3165856750
Short name T273
Test name
Test status
Simulation time 3341719670 ps
CPU time 16.72 seconds
Started Jun 22 06:11:28 PM PDT 24
Finished Jun 22 06:11:46 PM PDT 24
Peak memory 224684 kb
Host smart-ec34e9bb-ed55-4bdc-a0e6-30eee29b6665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165856750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3165856750
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1421351590
Short name T287
Test name
Test status
Simulation time 401745331 ps
CPU time 4.95 seconds
Started Jun 22 06:11:31 PM PDT 24
Finished Jun 22 06:11:36 PM PDT 24
Peak memory 224832 kb
Host smart-8a8ef377-9539-4319-8a9a-2d4cd7a524e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421351590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1421351590
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1996906722
Short name T929
Test name
Test status
Simulation time 1695946731 ps
CPU time 6.27 seconds
Started Jun 22 06:11:29 PM PDT 24
Finished Jun 22 06:11:36 PM PDT 24
Peak memory 240756 kb
Host smart-d2beaad6-9586-4758-9ebc-4f034601c5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996906722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1996906722
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1783348813
Short name T816
Test name
Test status
Simulation time 1849879745 ps
CPU time 8 seconds
Started Jun 22 06:11:32 PM PDT 24
Finished Jun 22 06:11:40 PM PDT 24
Peak memory 218936 kb
Host smart-276b2980-3b0e-45dd-852d-ac76e22e0ba3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1783348813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1783348813
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2448276600
Short name T65
Test name
Test status
Simulation time 12343073296 ps
CPU time 99.24 seconds
Started Jun 22 06:11:28 PM PDT 24
Finished Jun 22 06:13:08 PM PDT 24
Peak memory 251828 kb
Host smart-e7abc098-af07-4af4-a5db-db14e5ffa351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448276600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2448276600
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1866225604
Short name T920
Test name
Test status
Simulation time 16350166709 ps
CPU time 27.65 seconds
Started Jun 22 06:11:28 PM PDT 24
Finished Jun 22 06:11:57 PM PDT 24
Peak memory 216448 kb
Host smart-cece905c-37fc-407a-9161-554d02baac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866225604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1866225604
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1174965345
Short name T869
Test name
Test status
Simulation time 920927715 ps
CPU time 3.54 seconds
Started Jun 22 06:11:29 PM PDT 24
Finished Jun 22 06:11:33 PM PDT 24
Peak memory 216388 kb
Host smart-974747ae-2e0c-43c8-b658-7a44a082aa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174965345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1174965345
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3170014759
Short name T427
Test name
Test status
Simulation time 174017324 ps
CPU time 3.49 seconds
Started Jun 22 06:11:31 PM PDT 24
Finished Jun 22 06:11:35 PM PDT 24
Peak memory 216364 kb
Host smart-16c909dc-cfc6-488a-8def-0a198f9452f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170014759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3170014759
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2566986479
Short name T495
Test name
Test status
Simulation time 106770484 ps
CPU time 1.07 seconds
Started Jun 22 06:11:29 PM PDT 24
Finished Jun 22 06:11:31 PM PDT 24
Peak memory 207120 kb
Host smart-570e521c-cab1-4e12-9f3a-bdb2b87c10fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566986479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2566986479
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3762611622
Short name T241
Test name
Test status
Simulation time 29874432481 ps
CPU time 25.8 seconds
Started Jun 22 06:11:35 PM PDT 24
Finished Jun 22 06:12:01 PM PDT 24
Peak memory 233008 kb
Host smart-6eb3a390-732e-42df-97c3-9bd14ad2c980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762611622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3762611622
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1629383082
Short name T478
Test name
Test status
Simulation time 12727873 ps
CPU time 0.73 seconds
Started Jun 22 06:11:37 PM PDT 24
Finished Jun 22 06:11:38 PM PDT 24
Peak memory 205520 kb
Host smart-8d6b6e86-83e3-4f99-aa17-074437098bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629383082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1629383082
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1434526953
Short name T92
Test name
Test status
Simulation time 1873289262 ps
CPU time 20.2 seconds
Started Jun 22 06:11:35 PM PDT 24
Finished Jun 22 06:11:55 PM PDT 24
Peak memory 224680 kb
Host smart-35842c11-f732-4ff0-97ee-cc8dcce7c26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434526953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1434526953
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.134692040
Short name T934
Test name
Test status
Simulation time 14183487 ps
CPU time 0.78 seconds
Started Jun 22 06:11:29 PM PDT 24
Finished Jun 22 06:11:31 PM PDT 24
Peak memory 205668 kb
Host smart-3bdc74ee-d51d-46b8-ba8e-67195b745483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134692040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.134692040
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1326299326
Short name T386
Test name
Test status
Simulation time 27037500812 ps
CPU time 207.06 seconds
Started Jun 22 06:11:35 PM PDT 24
Finished Jun 22 06:15:02 PM PDT 24
Peak memory 249380 kb
Host smart-5ee90eef-3d59-4d19-9b0f-a5e03a37599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326299326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1326299326
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1882447762
Short name T171
Test name
Test status
Simulation time 58127304961 ps
CPU time 174.81 seconds
Started Jun 22 06:11:38 PM PDT 24
Finished Jun 22 06:14:33 PM PDT 24
Peak memory 255204 kb
Host smart-16eaeda3-824b-4893-8b29-7f77632061d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882447762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1882447762
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4188296078
Short name T177
Test name
Test status
Simulation time 2278874663 ps
CPU time 33.97 seconds
Started Jun 22 06:11:36 PM PDT 24
Finished Jun 22 06:12:11 PM PDT 24
Peak memory 224812 kb
Host smart-0dc3ec88-7324-4f6a-8a79-fbc1ea360ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188296078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4188296078
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4192854221
Short name T755
Test name
Test status
Simulation time 32289966 ps
CPU time 2.37 seconds
Started Jun 22 06:11:35 PM PDT 24
Finished Jun 22 06:11:38 PM PDT 24
Peak memory 223932 kb
Host smart-555468b3-bdb9-454f-9088-bf8ebaf29c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192854221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4192854221
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.547906031
Short name T766
Test name
Test status
Simulation time 1034808625 ps
CPU time 8.57 seconds
Started Jun 22 06:11:38 PM PDT 24
Finished Jun 22 06:11:47 PM PDT 24
Peak memory 232876 kb
Host smart-e925919b-f88b-4841-987b-bdd13fd41f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547906031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.547906031
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.62540772
Short name T652
Test name
Test status
Simulation time 1098883886 ps
CPU time 6.48 seconds
Started Jun 22 06:11:37 PM PDT 24
Finished Jun 22 06:11:44 PM PDT 24
Peak memory 232740 kb
Host smart-fc820f41-6488-492f-853b-6b64b5fa302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62540772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.62540772
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3571018440
Short name T773
Test name
Test status
Simulation time 2119639671 ps
CPU time 12.69 seconds
Started Jun 22 06:11:36 PM PDT 24
Finished Jun 22 06:11:50 PM PDT 24
Peak memory 224732 kb
Host smart-41463439-1f0a-48c4-bc68-855d10032e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571018440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3571018440
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1136476164
Short name T681
Test name
Test status
Simulation time 618319776 ps
CPU time 6.31 seconds
Started Jun 22 06:11:31 PM PDT 24
Finished Jun 22 06:11:37 PM PDT 24
Peak memory 228552 kb
Host smart-67c8854c-6780-412e-a9ad-0b60443bc74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136476164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1136476164
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.875555621
Short name T699
Test name
Test status
Simulation time 213399541 ps
CPU time 3.41 seconds
Started Jun 22 06:11:38 PM PDT 24
Finished Jun 22 06:11:42 PM PDT 24
Peak memory 219584 kb
Host smart-b9963292-0440-4474-a5cb-dc22b1da0d8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=875555621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.875555621
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.800600709
Short name T857
Test name
Test status
Simulation time 48490292354 ps
CPU time 118.88 seconds
Started Jun 22 06:11:39 PM PDT 24
Finished Jun 22 06:13:38 PM PDT 24
Peak memory 250496 kb
Host smart-914e694a-fbfd-40fd-8365-59d431c20ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800600709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.800600709
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.277429030
Short name T886
Test name
Test status
Simulation time 178061932 ps
CPU time 2.23 seconds
Started Jun 22 06:11:28 PM PDT 24
Finished Jun 22 06:11:30 PM PDT 24
Peak memory 216448 kb
Host smart-4ee1204b-84f5-4a5f-8e35-b882073f4b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277429030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.277429030
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3709703167
Short name T647
Test name
Test status
Simulation time 3822266011 ps
CPU time 6.41 seconds
Started Jun 22 06:11:32 PM PDT 24
Finished Jun 22 06:11:39 PM PDT 24
Peak memory 216552 kb
Host smart-35307f7a-d231-444c-bf5a-41670c5fcc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709703167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3709703167
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.657777313
Short name T599
Test name
Test status
Simulation time 53730769 ps
CPU time 1.19 seconds
Started Jun 22 06:11:29 PM PDT 24
Finished Jun 22 06:11:31 PM PDT 24
Peak memory 216224 kb
Host smart-eb5e9ced-85b8-4e98-9e28-8ee8da43e882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657777313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.657777313
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3395379312
Short name T488
Test name
Test status
Simulation time 42883577 ps
CPU time 0.81 seconds
Started Jun 22 06:11:26 PM PDT 24
Finished Jun 22 06:11:28 PM PDT 24
Peak memory 206104 kb
Host smart-2c126ab1-0506-4ce9-895d-0d056afbc86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395379312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3395379312
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1793688476
Short name T852
Test name
Test status
Simulation time 2954032873 ps
CPU time 8.63 seconds
Started Jun 22 06:11:35 PM PDT 24
Finished Jun 22 06:11:44 PM PDT 24
Peak memory 224772 kb
Host smart-17abc0c7-b806-4572-8558-8067801a6ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793688476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1793688476
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.967074617
Short name T340
Test name
Test status
Simulation time 41716945 ps
CPU time 0.72 seconds
Started Jun 22 06:11:40 PM PDT 24
Finished Jun 22 06:11:41 PM PDT 24
Peak memory 205488 kb
Host smart-1cadac30-bd7f-4066-b054-178c9b191bf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967074617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.967074617
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.443585682
Short name T585
Test name
Test status
Simulation time 2924265954 ps
CPU time 27.8 seconds
Started Jun 22 06:11:36 PM PDT 24
Finished Jun 22 06:12:05 PM PDT 24
Peak memory 233016 kb
Host smart-72b9543d-8b46-463d-b033-39895a64aff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443585682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.443585682
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3981450123
Short name T385
Test name
Test status
Simulation time 19618049 ps
CPU time 0.82 seconds
Started Jun 22 06:11:36 PM PDT 24
Finished Jun 22 06:11:37 PM PDT 24
Peak memory 206752 kb
Host smart-7ebb8012-2c82-4c2f-9bf4-e009cbfbb6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981450123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3981450123
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1010394177
Short name T813
Test name
Test status
Simulation time 15185687831 ps
CPU time 16.41 seconds
Started Jun 22 06:11:36 PM PDT 24
Finished Jun 22 06:11:53 PM PDT 24
Peak memory 224736 kb
Host smart-108e0428-ef20-4196-a8f4-570a8838a26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010394177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1010394177
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3254962232
Short name T324
Test name
Test status
Simulation time 4207584867 ps
CPU time 44.56 seconds
Started Jun 22 06:11:42 PM PDT 24
Finished Jun 22 06:12:27 PM PDT 24
Peak memory 236444 kb
Host smart-f783442d-eb24-44f4-b6fb-400af67ca297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254962232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3254962232
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2171983534
Short name T25
Test name
Test status
Simulation time 1996595880 ps
CPU time 17.98 seconds
Started Jun 22 06:11:36 PM PDT 24
Finished Jun 22 06:11:55 PM PDT 24
Peak memory 232888 kb
Host smart-db549fbe-d945-415b-8cb3-484e8057e073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171983534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2171983534
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3891366274
Short name T663
Test name
Test status
Simulation time 6544631398 ps
CPU time 25.03 seconds
Started Jun 22 06:11:34 PM PDT 24
Finished Jun 22 06:11:59 PM PDT 24
Peak memory 227296 kb
Host smart-e251d609-1706-4910-9b02-88cdfe050648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891366274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3891366274
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2112319152
Short name T640
Test name
Test status
Simulation time 2077946212 ps
CPU time 7.48 seconds
Started Jun 22 06:11:34 PM PDT 24
Finished Jun 22 06:11:42 PM PDT 24
Peak memory 232824 kb
Host smart-677b4f37-e595-4d29-b5cb-0de01f12e392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112319152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2112319152
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2401508683
Short name T436
Test name
Test status
Simulation time 2784648293 ps
CPU time 11.7 seconds
Started Jun 22 06:11:35 PM PDT 24
Finished Jun 22 06:11:48 PM PDT 24
Peak memory 240900 kb
Host smart-554030b3-57bf-41f1-8911-a8339e451749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401508683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2401508683
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3588752251
Short name T730
Test name
Test status
Simulation time 2747156451 ps
CPU time 11.33 seconds
Started Jun 22 06:11:37 PM PDT 24
Finished Jun 22 06:11:49 PM PDT 24
Peak memory 223432 kb
Host smart-4431ef1b-a80c-47c3-80d3-dc00a13fa322
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3588752251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3588752251
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.4097814041
Short name T894
Test name
Test status
Simulation time 32158732 ps
CPU time 0.74 seconds
Started Jun 22 06:11:36 PM PDT 24
Finished Jun 22 06:11:38 PM PDT 24
Peak memory 205820 kb
Host smart-06562ead-1b1c-4630-bc71-8ed9a392e1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097814041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.4097814041
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.523728992
Short name T961
Test name
Test status
Simulation time 139375202 ps
CPU time 1.47 seconds
Started Jun 22 06:11:34 PM PDT 24
Finished Jun 22 06:11:36 PM PDT 24
Peak memory 208080 kb
Host smart-bdb0bb90-2fe3-461b-825e-612d872e2e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523728992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.523728992
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2092223642
Short name T873
Test name
Test status
Simulation time 17285511 ps
CPU time 0.83 seconds
Started Jun 22 06:11:36 PM PDT 24
Finished Jun 22 06:11:38 PM PDT 24
Peak memory 206084 kb
Host smart-ba5be553-c569-4fab-921f-1e0324800e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092223642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2092223642
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2486215113
Short name T454
Test name
Test status
Simulation time 138203749 ps
CPU time 1 seconds
Started Jun 22 06:11:36 PM PDT 24
Finished Jun 22 06:11:38 PM PDT 24
Peak memory 206092 kb
Host smart-ed0a3a38-90e1-4a5d-bba3-808dad131929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486215113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2486215113
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2286935468
Short name T284
Test name
Test status
Simulation time 7252829140 ps
CPU time 7.7 seconds
Started Jun 22 06:11:37 PM PDT 24
Finished Jun 22 06:11:45 PM PDT 24
Peak memory 233020 kb
Host smart-0ebef705-fa6f-4e93-a7a8-211d3d91d0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286935468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2286935468
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.190396893
Short name T891
Test name
Test status
Simulation time 17663969 ps
CPU time 0.76 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:11:49 PM PDT 24
Peak memory 205528 kb
Host smart-11e2af5d-6b4d-4a76-8661-14b49b240b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190396893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.190396893
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.711960131
Short name T382
Test name
Test status
Simulation time 35995685 ps
CPU time 2.46 seconds
Started Jun 22 06:11:41 PM PDT 24
Finished Jun 22 06:11:43 PM PDT 24
Peak memory 232892 kb
Host smart-58994559-ed40-4b75-917b-52c0d71050b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711960131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.711960131
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.943697645
Short name T353
Test name
Test status
Simulation time 19826746 ps
CPU time 0.77 seconds
Started Jun 22 06:11:43 PM PDT 24
Finished Jun 22 06:11:45 PM PDT 24
Peak memory 205728 kb
Host smart-d9c39918-cd2d-4ddd-af8c-2433d14ee9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943697645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.943697645
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.396656737
Short name T956
Test name
Test status
Simulation time 2547983214 ps
CPU time 25.06 seconds
Started Jun 22 06:11:42 PM PDT 24
Finished Jun 22 06:12:07 PM PDT 24
Peak memory 252516 kb
Host smart-6681db3a-42c6-4e0f-9501-5aa297d362ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396656737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.396656737
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2702969726
Short name T40
Test name
Test status
Simulation time 16607901068 ps
CPU time 131.74 seconds
Started Jun 22 06:11:42 PM PDT 24
Finished Jun 22 06:13:54 PM PDT 24
Peak memory 250884 kb
Host smart-6497249f-134e-4de8-9a67-09e7c2694bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702969726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2702969726
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2676172772
Short name T242
Test name
Test status
Simulation time 133577554389 ps
CPU time 59.87 seconds
Started Jun 22 06:11:47 PM PDT 24
Finished Jun 22 06:12:47 PM PDT 24
Peak memory 240268 kb
Host smart-9d948ab9-d415-45f8-a6b4-ad3412004b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676172772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2676172772
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1820778675
Short name T365
Test name
Test status
Simulation time 512606047 ps
CPU time 6.91 seconds
Started Jun 22 06:11:43 PM PDT 24
Finished Jun 22 06:11:50 PM PDT 24
Peak memory 233144 kb
Host smart-ec855088-5d4c-4190-b894-ce967eb12574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820778675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1820778675
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3183506652
Short name T893
Test name
Test status
Simulation time 702631308 ps
CPU time 8.95 seconds
Started Jun 22 06:11:40 PM PDT 24
Finished Jun 22 06:11:49 PM PDT 24
Peak memory 232892 kb
Host smart-7179cc19-06f2-431e-802a-6a86f88dc5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183506652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3183506652
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1493087045
Short name T711
Test name
Test status
Simulation time 13831761264 ps
CPU time 31.42 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:12:20 PM PDT 24
Peak memory 233044 kb
Host smart-e1c1c63d-3879-49ba-a2d0-5e666e7f74d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493087045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1493087045
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3321145451
Short name T588
Test name
Test status
Simulation time 4905083895 ps
CPU time 6.9 seconds
Started Jun 22 06:11:45 PM PDT 24
Finished Jun 22 06:11:52 PM PDT 24
Peak memory 232996 kb
Host smart-4645a0fd-7fb2-445e-b6c4-67013417ed14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321145451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3321145451
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3481233869
Short name T354
Test name
Test status
Simulation time 5058208973 ps
CPU time 15.36 seconds
Started Jun 22 06:11:44 PM PDT 24
Finished Jun 22 06:12:00 PM PDT 24
Peak memory 241200 kb
Host smart-bff7bfcc-018d-4b1d-93f6-5da4072c96f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481233869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3481233869
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2556090647
Short name T410
Test name
Test status
Simulation time 2985399711 ps
CPU time 9.73 seconds
Started Jun 22 06:11:43 PM PDT 24
Finished Jun 22 06:11:54 PM PDT 24
Peak memory 223360 kb
Host smart-117db394-42b1-4b47-8272-b935a3e04765
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2556090647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2556090647
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3414907538
Short name T801
Test name
Test status
Simulation time 20449468621 ps
CPU time 26.86 seconds
Started Jun 22 06:11:43 PM PDT 24
Finished Jun 22 06:12:10 PM PDT 24
Peak memory 220456 kb
Host smart-c4a17a8a-bd83-4066-a5d2-f2fa4866a146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414907538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3414907538
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2511761191
Short name T639
Test name
Test status
Simulation time 5298960670 ps
CPU time 26.38 seconds
Started Jun 22 06:11:43 PM PDT 24
Finished Jun 22 06:12:11 PM PDT 24
Peak memory 216744 kb
Host smart-302f1332-214f-4698-9cb4-a5a0810bfe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511761191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2511761191
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4275309585
Short name T445
Test name
Test status
Simulation time 892615968 ps
CPU time 2.51 seconds
Started Jun 22 06:11:42 PM PDT 24
Finished Jun 22 06:11:45 PM PDT 24
Peak memory 216356 kb
Host smart-17b7e24b-ab56-4a6e-999f-d62b002fedcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275309585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4275309585
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.4051650371
Short name T566
Test name
Test status
Simulation time 71555099 ps
CPU time 0.88 seconds
Started Jun 22 06:11:42 PM PDT 24
Finished Jun 22 06:11:44 PM PDT 24
Peak memory 206900 kb
Host smart-20a202ba-bab5-49cc-98b4-c7122a652ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051650371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4051650371
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3659035747
Short name T725
Test name
Test status
Simulation time 93496207 ps
CPU time 0.81 seconds
Started Jun 22 06:11:43 PM PDT 24
Finished Jun 22 06:11:45 PM PDT 24
Peak memory 206096 kb
Host smart-1eb9ae5d-8d6d-4219-8544-a876cc56adcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659035747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3659035747
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2960999750
Short name T666
Test name
Test status
Simulation time 154928359 ps
CPU time 2.69 seconds
Started Jun 22 06:11:43 PM PDT 24
Finished Jun 22 06:11:46 PM PDT 24
Peak memory 224640 kb
Host smart-6ea1321b-8241-4844-b4c9-bd9a8bb0b044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960999750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2960999750
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.478929937
Short name T791
Test name
Test status
Simulation time 17663705 ps
CPU time 0.7 seconds
Started Jun 22 06:11:42 PM PDT 24
Finished Jun 22 06:11:44 PM PDT 24
Peak memory 205452 kb
Host smart-5e3368af-3cac-4850-bf8d-de9f6172a27e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478929937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.478929937
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1183900855
Short name T709
Test name
Test status
Simulation time 309084195 ps
CPU time 3.56 seconds
Started Jun 22 06:11:40 PM PDT 24
Finished Jun 22 06:11:44 PM PDT 24
Peak memory 232900 kb
Host smart-3637d9a0-ecbe-42ad-ad50-07589821c6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183900855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1183900855
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.137900902
Short name T901
Test name
Test status
Simulation time 20389032 ps
CPU time 0.77 seconds
Started Jun 22 06:11:44 PM PDT 24
Finished Jun 22 06:11:45 PM PDT 24
Peak memory 205728 kb
Host smart-03232a10-b59f-4d29-9bf2-c3833083633f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137900902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.137900902
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2761605960
Short name T306
Test name
Test status
Simulation time 7524690660 ps
CPU time 90.32 seconds
Started Jun 22 06:11:44 PM PDT 24
Finished Jun 22 06:13:15 PM PDT 24
Peak memory 265736 kb
Host smart-ada3995b-8ad5-45c1-a8d5-385345989e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761605960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2761605960
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.730369018
Short name T924
Test name
Test status
Simulation time 20444250708 ps
CPU time 31.51 seconds
Started Jun 22 06:11:43 PM PDT 24
Finished Jun 22 06:12:16 PM PDT 24
Peak memory 219852 kb
Host smart-82f96df0-6a6a-42cd-95cc-34ad81ceabca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730369018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.730369018
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1314695046
Short name T311
Test name
Test status
Simulation time 4422500398 ps
CPU time 20.05 seconds
Started Jun 22 06:11:44 PM PDT 24
Finished Jun 22 06:12:04 PM PDT 24
Peak memory 241132 kb
Host smart-6e9379f1-69fa-4fc0-ba18-9b3f5a5646dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314695046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1314695046
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.493752796
Short name T258
Test name
Test status
Simulation time 675834993 ps
CPU time 3.8 seconds
Started Jun 22 06:11:43 PM PDT 24
Finished Jun 22 06:11:47 PM PDT 24
Peak memory 224584 kb
Host smart-0e613e6c-8fd3-420d-a04a-98d26de0211b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493752796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.493752796
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1922526947
Short name T359
Test name
Test status
Simulation time 17500363309 ps
CPU time 194.18 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:15:03 PM PDT 24
Peak memory 240600 kb
Host smart-b2c65c69-bd26-4095-91ff-defc8ddcd509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922526947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1922526947
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2510320716
Short name T900
Test name
Test status
Simulation time 38982903 ps
CPU time 2.44 seconds
Started Jun 22 06:11:43 PM PDT 24
Finished Jun 22 06:11:46 PM PDT 24
Peak memory 232484 kb
Host smart-55c9213a-937c-462c-abdb-65e19af16a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510320716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2510320716
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.371333675
Short name T197
Test name
Test status
Simulation time 4087187738 ps
CPU time 8.12 seconds
Started Jun 22 06:11:44 PM PDT 24
Finished Jun 22 06:11:53 PM PDT 24
Peak memory 232936 kb
Host smart-69dbb4c5-0314-44a8-89dc-59a4ec949c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371333675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.371333675
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3618664770
Short name T446
Test name
Test status
Simulation time 628823056 ps
CPU time 11.1 seconds
Started Jun 22 06:11:41 PM PDT 24
Finished Jun 22 06:11:53 PM PDT 24
Peak memory 220364 kb
Host smart-0b0f9859-0ede-4ab4-8cd8-adcc5aef014e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3618664770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3618664770
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1686268440
Short name T298
Test name
Test status
Simulation time 16043648832 ps
CPU time 185.76 seconds
Started Jun 22 06:11:44 PM PDT 24
Finished Jun 22 06:14:50 PM PDT 24
Peak memory 271876 kb
Host smart-0b85b541-58f8-4192-bd14-1d68bc394487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686268440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1686268440
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4097908585
Short name T323
Test name
Test status
Simulation time 7461673370 ps
CPU time 34.62 seconds
Started Jun 22 06:11:41 PM PDT 24
Finished Jun 22 06:12:16 PM PDT 24
Peak memory 216524 kb
Host smart-14432803-850f-42ef-975f-191bdd02906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097908585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4097908585
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1081385035
Short name T341
Test name
Test status
Simulation time 2954424318 ps
CPU time 11.8 seconds
Started Jun 22 06:11:42 PM PDT 24
Finished Jun 22 06:11:54 PM PDT 24
Peak memory 216472 kb
Host smart-274e9a19-4d30-4fad-8227-86ccc57b9d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081385035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1081385035
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1627542249
Short name T890
Test name
Test status
Simulation time 126515638 ps
CPU time 1.71 seconds
Started Jun 22 06:11:42 PM PDT 24
Finished Jun 22 06:11:44 PM PDT 24
Peak memory 216392 kb
Host smart-c7682e16-3afd-4476-9634-a8e53cf16170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627542249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1627542249
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1494767219
Short name T715
Test name
Test status
Simulation time 194010097 ps
CPU time 0.71 seconds
Started Jun 22 06:11:42 PM PDT 24
Finished Jun 22 06:11:43 PM PDT 24
Peak memory 206096 kb
Host smart-b119b801-ad28-41dc-8ae9-0a0218e0ce10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494767219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1494767219
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2505202276
Short name T263
Test name
Test status
Simulation time 2834977300 ps
CPU time 8.64 seconds
Started Jun 22 06:11:47 PM PDT 24
Finished Jun 22 06:11:57 PM PDT 24
Peak memory 224816 kb
Host smart-10e458c5-718d-4849-9410-6c5e32aaa531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505202276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2505202276
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2538187384
Short name T707
Test name
Test status
Simulation time 10968679 ps
CPU time 0.73 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:11:50 PM PDT 24
Peak memory 205808 kb
Host smart-bdf1d84f-9fed-480e-9c1f-f675a61faf97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538187384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2538187384
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.135372951
Short name T530
Test name
Test status
Simulation time 222024892 ps
CPU time 3.67 seconds
Started Jun 22 06:11:47 PM PDT 24
Finished Jun 22 06:11:51 PM PDT 24
Peak memory 224716 kb
Host smart-b4e15b57-630b-4cd9-9099-a6a6f5572881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135372951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.135372951
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1045615752
Short name T457
Test name
Test status
Simulation time 78159084 ps
CPU time 0.8 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:11:50 PM PDT 24
Peak memory 207016 kb
Host smart-ac5ccbe4-9644-4062-87a8-e47c6ec78440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045615752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1045615752
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3335948708
Short name T234
Test name
Test status
Simulation time 65253053562 ps
CPU time 111.85 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:13:41 PM PDT 24
Peak memory 249308 kb
Host smart-07d2a65c-9789-4ffb-aef6-ad1ebaeca24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335948708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3335948708
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2784034965
Short name T916
Test name
Test status
Simulation time 14278731463 ps
CPU time 152.69 seconds
Started Jun 22 06:11:50 PM PDT 24
Finished Jun 22 06:14:24 PM PDT 24
Peak memory 250404 kb
Host smart-333ca80b-4324-4f0b-9914-0e55b1f37c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784034965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2784034965
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1951436117
Short name T751
Test name
Test status
Simulation time 9404193509 ps
CPU time 58.42 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:12:47 PM PDT 24
Peak memory 249440 kb
Host smart-12607f27-f600-460f-9796-75ae8ec0621f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951436117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1951436117
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3945842375
Short name T645
Test name
Test status
Simulation time 1127465085 ps
CPU time 19.67 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:12:08 PM PDT 24
Peak memory 232824 kb
Host smart-5e8ce391-ea69-4b7f-96ea-13a4c96a350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945842375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3945842375
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1503114757
Short name T544
Test name
Test status
Simulation time 1923456707 ps
CPU time 17.71 seconds
Started Jun 22 06:11:50 PM PDT 24
Finished Jun 22 06:12:08 PM PDT 24
Peak memory 232836 kb
Host smart-782fa0e6-01ce-4e87-9f4c-a0300cd62afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503114757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1503114757
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1212002735
Short name T797
Test name
Test status
Simulation time 599899673 ps
CPU time 10.99 seconds
Started Jun 22 06:11:47 PM PDT 24
Finished Jun 22 06:11:59 PM PDT 24
Peak memory 224628 kb
Host smart-ae47ee55-3f31-44b8-bc63-f181baa95b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212002735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1212002735
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.900966034
Short name T856
Test name
Test status
Simulation time 21989025555 ps
CPU time 8.92 seconds
Started Jun 22 06:11:51 PM PDT 24
Finished Jun 22 06:12:00 PM PDT 24
Peak memory 240904 kb
Host smart-b1236dbf-254c-43f0-9718-0cc58c0a57ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900966034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.900966034
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.4111869744
Short name T58
Test name
Test status
Simulation time 446184700 ps
CPU time 3.62 seconds
Started Jun 22 06:11:51 PM PDT 24
Finished Jun 22 06:11:55 PM PDT 24
Peak memory 224708 kb
Host smart-69add654-6b47-4a1a-98f8-9dc4a5c38532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111869744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4111869744
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.619154422
Short name T936
Test name
Test status
Simulation time 598853343 ps
CPU time 6.49 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:11:55 PM PDT 24
Peak memory 220556 kb
Host smart-e959efff-499a-44c2-b5fa-90b21757418c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=619154422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.619154422
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.161874526
Short name T631
Test name
Test status
Simulation time 37600990 ps
CPU time 0.87 seconds
Started Jun 22 06:11:46 PM PDT 24
Finished Jun 22 06:11:47 PM PDT 24
Peak memory 205724 kb
Host smart-30c052f3-c458-4e5e-ac06-f2e2412a159a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161874526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.161874526
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1626688611
Short name T580
Test name
Test status
Simulation time 770100057 ps
CPU time 12.48 seconds
Started Jun 22 06:11:47 PM PDT 24
Finished Jun 22 06:12:01 PM PDT 24
Peak memory 216672 kb
Host smart-8f40bcd1-f33d-4dee-97f0-41ae4def3bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626688611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1626688611
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.432070222
Short name T960
Test name
Test status
Simulation time 49364880 ps
CPU time 0.76 seconds
Started Jun 22 06:11:47 PM PDT 24
Finished Jun 22 06:11:48 PM PDT 24
Peak memory 205760 kb
Host smart-b392a190-e713-4142-85c5-3e43c4aa3f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432070222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.432070222
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2821863430
Short name T616
Test name
Test status
Simulation time 12740659 ps
CPU time 0.69 seconds
Started Jun 22 06:11:49 PM PDT 24
Finished Jun 22 06:11:51 PM PDT 24
Peak memory 205716 kb
Host smart-35a05c7f-9f87-4b23-9049-1fa4b7461b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821863430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2821863430
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2323633936
Short name T402
Test name
Test status
Simulation time 68017728 ps
CPU time 0.95 seconds
Started Jun 22 06:11:49 PM PDT 24
Finished Jun 22 06:11:51 PM PDT 24
Peak memory 206100 kb
Host smart-8d8fb548-42a6-484b-ad38-2b557eaa4233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323633936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2323633936
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1780592855
Short name T476
Test name
Test status
Simulation time 672792074 ps
CPU time 6.44 seconds
Started Jun 22 06:11:51 PM PDT 24
Finished Jun 22 06:11:58 PM PDT 24
Peak memory 224700 kb
Host smart-e85ac701-fc24-49a1-b2dd-ea68c1e288a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780592855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1780592855
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3749905482
Short name T925
Test name
Test status
Simulation time 20868218 ps
CPU time 0.74 seconds
Started Jun 22 06:09:41 PM PDT 24
Finished Jun 22 06:09:43 PM PDT 24
Peak memory 205500 kb
Host smart-cc14eb43-30bc-41fa-ba09-14aaaeb87629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749905482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
749905482
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2899711934
Short name T384
Test name
Test status
Simulation time 525919621 ps
CPU time 3.27 seconds
Started Jun 22 06:09:37 PM PDT 24
Finished Jun 22 06:09:41 PM PDT 24
Peak memory 224672 kb
Host smart-3f0c6029-9a00-4614-8f08-e218e2c0a9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899711934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2899711934
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.677788017
Short name T597
Test name
Test status
Simulation time 15904988 ps
CPU time 0.76 seconds
Started Jun 22 06:09:36 PM PDT 24
Finished Jun 22 06:09:37 PM PDT 24
Peak memory 206760 kb
Host smart-d0aff0e3-6013-4b12-8324-ff4dba8cec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677788017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.677788017
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1116202732
Short name T218
Test name
Test status
Simulation time 9922581317 ps
CPU time 96.26 seconds
Started Jun 22 06:09:34 PM PDT 24
Finished Jun 22 06:11:11 PM PDT 24
Peak memory 263696 kb
Host smart-580eea93-a4e3-47e8-b962-97b3cfcc310f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116202732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1116202732
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2331830069
Short name T246
Test name
Test status
Simulation time 6265515703 ps
CPU time 90.98 seconds
Started Jun 22 06:09:45 PM PDT 24
Finished Jun 22 06:11:16 PM PDT 24
Peak memory 268032 kb
Host smart-a1f263c6-06de-4874-8a9b-b81350b4caa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331830069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2331830069
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.239960042
Short name T316
Test name
Test status
Simulation time 2475648648 ps
CPU time 38.17 seconds
Started Jun 22 06:09:39 PM PDT 24
Finished Jun 22 06:10:18 PM PDT 24
Peak memory 249516 kb
Host smart-e43cd788-70a6-42f4-81b3-db1a56e0d9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239960042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.239960042
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3492424715
Short name T761
Test name
Test status
Simulation time 8512091763 ps
CPU time 25.92 seconds
Started Jun 22 06:09:39 PM PDT 24
Finished Jun 22 06:10:06 PM PDT 24
Peak memory 224760 kb
Host smart-c6844df3-33eb-47ec-bda1-4f9216f7ff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492424715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3492424715
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1702038729
Short name T561
Test name
Test status
Simulation time 11234891035 ps
CPU time 70.22 seconds
Started Jun 22 06:09:37 PM PDT 24
Finished Jun 22 06:10:48 PM PDT 24
Peak memory 224680 kb
Host smart-ec7144cc-4c07-48d6-8950-2a187825407b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702038729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1702038729
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.233800356
Short name T477
Test name
Test status
Simulation time 326045517 ps
CPU time 7.16 seconds
Started Jun 22 06:09:35 PM PDT 24
Finished Jun 22 06:09:43 PM PDT 24
Peak memory 232880 kb
Host smart-0f133154-3d10-472c-bbba-61e97c89c9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233800356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
233800356
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.996003118
Short name T23
Test name
Test status
Simulation time 2355797725 ps
CPU time 4.84 seconds
Started Jun 22 06:09:39 PM PDT 24
Finished Jun 22 06:09:44 PM PDT 24
Peak memory 224752 kb
Host smart-df7f282b-bb37-4801-8ab0-0bddfebc9c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996003118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.996003118
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1203243601
Short name T47
Test name
Test status
Simulation time 1243794675 ps
CPU time 5.54 seconds
Started Jun 22 06:09:36 PM PDT 24
Finished Jun 22 06:09:43 PM PDT 24
Peak memory 223352 kb
Host smart-54c54121-ba32-48fd-9556-079624a3ad87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1203243601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1203243601
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2714433167
Short name T79
Test name
Test status
Simulation time 130911379 ps
CPU time 1.04 seconds
Started Jun 22 06:09:39 PM PDT 24
Finished Jun 22 06:09:41 PM PDT 24
Peak memory 235828 kb
Host smart-b2067cc6-215c-42d5-89b6-e933eaf769e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714433167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2714433167
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2359973961
Short name T329
Test name
Test status
Simulation time 4855454117 ps
CPU time 45.51 seconds
Started Jun 22 06:09:36 PM PDT 24
Finished Jun 22 06:10:23 PM PDT 24
Peak memory 252692 kb
Host smart-1d1ac9d1-37e5-4874-818b-6e84cfb94b8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359973961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2359973961
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2666462222
Short name T906
Test name
Test status
Simulation time 1024719578 ps
CPU time 3.63 seconds
Started Jun 22 06:09:39 PM PDT 24
Finished Jun 22 06:09:43 PM PDT 24
Peak memory 216420 kb
Host smart-e038e3fd-fc69-4d42-85a1-0da1793dbdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666462222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2666462222
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1350932205
Short name T912
Test name
Test status
Simulation time 11006990238 ps
CPU time 13.15 seconds
Started Jun 22 06:09:46 PM PDT 24
Finished Jun 22 06:09:59 PM PDT 24
Peak memory 216504 kb
Host smart-8412c697-461d-4790-8979-3415eca214b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350932205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1350932205
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2988208654
Short name T946
Test name
Test status
Simulation time 35326702 ps
CPU time 1.14 seconds
Started Jun 22 06:09:34 PM PDT 24
Finished Jun 22 06:09:36 PM PDT 24
Peak memory 216336 kb
Host smart-1bb37ca3-3771-47e8-bdd7-f4cecd354652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988208654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2988208654
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2843049634
Short name T603
Test name
Test status
Simulation time 222405425 ps
CPU time 0.88 seconds
Started Jun 22 06:09:36 PM PDT 24
Finished Jun 22 06:09:38 PM PDT 24
Peak memory 206260 kb
Host smart-0c561daa-c774-48a5-89e2-4471cf025c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843049634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2843049634
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.132328977
Short name T815
Test name
Test status
Simulation time 3955236363 ps
CPU time 9.86 seconds
Started Jun 22 06:09:35 PM PDT 24
Finished Jun 22 06:09:45 PM PDT 24
Peak memory 239980 kb
Host smart-c74d2a1e-d7ee-4913-a314-09969514a872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132328977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.132328977
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2172841418
Short name T522
Test name
Test status
Simulation time 12122914 ps
CPU time 0.79 seconds
Started Jun 22 06:11:56 PM PDT 24
Finished Jun 22 06:11:57 PM PDT 24
Peak memory 205520 kb
Host smart-395e06e1-aca4-4a79-b653-0df3129d87a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172841418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2172841418
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2481287239
Short name T261
Test name
Test status
Simulation time 195698554 ps
CPU time 3.37 seconds
Started Jun 22 06:11:49 PM PDT 24
Finished Jun 22 06:11:53 PM PDT 24
Peak memory 224700 kb
Host smart-81897c02-5b5b-455d-a064-3b23dd594ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481287239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2481287239
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3981963028
Short name T344
Test name
Test status
Simulation time 73031963 ps
CPU time 0.82 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:11:50 PM PDT 24
Peak memory 206756 kb
Host smart-4185035a-1c95-49e6-bb8a-b1974dc87c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981963028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3981963028
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2911720326
Short name T192
Test name
Test status
Simulation time 11576397134 ps
CPU time 79.6 seconds
Started Jun 22 06:11:57 PM PDT 24
Finished Jun 22 06:13:17 PM PDT 24
Peak memory 241160 kb
Host smart-95676f64-e865-4b4f-89fa-07ca0be137f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911720326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2911720326
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1950490570
Short name T190
Test name
Test status
Simulation time 21950806871 ps
CPU time 126.52 seconds
Started Jun 22 06:11:55 PM PDT 24
Finished Jun 22 06:14:02 PM PDT 24
Peak memory 273632 kb
Host smart-1f0e086a-0d9e-4c08-984a-d336c12e9125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950490570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1950490570
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.562309805
Short name T53
Test name
Test status
Simulation time 54709003289 ps
CPU time 234.43 seconds
Started Jun 22 06:11:55 PM PDT 24
Finished Jun 22 06:15:50 PM PDT 24
Peak memory 256716 kb
Host smart-17d6fdf1-cd2f-491a-be6d-235a25700415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562309805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.562309805
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2711849543
Short name T48
Test name
Test status
Simulation time 653367219 ps
CPU time 15.47 seconds
Started Jun 22 06:11:50 PM PDT 24
Finished Jun 22 06:12:06 PM PDT 24
Peak memory 232852 kb
Host smart-a3e8167a-30a1-4702-aca8-f3806a54c893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711849543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2711849543
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3102795622
Short name T553
Test name
Test status
Simulation time 1822247137 ps
CPU time 16.64 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:12:06 PM PDT 24
Peak memory 224636 kb
Host smart-1badce5b-7aa5-49c7-91ba-b692c0cdcce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102795622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3102795622
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1319575172
Short name T280
Test name
Test status
Simulation time 18144517117 ps
CPU time 33.65 seconds
Started Jun 22 06:11:47 PM PDT 24
Finished Jun 22 06:12:22 PM PDT 24
Peak memory 232960 kb
Host smart-69c06348-1f9b-43f5-b967-b43446f47906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319575172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1319575172
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.980874354
Short name T141
Test name
Test status
Simulation time 6048364860 ps
CPU time 9.28 seconds
Started Jun 22 06:11:51 PM PDT 24
Finished Jun 22 06:12:01 PM PDT 24
Peak memory 249176 kb
Host smart-f0c6100b-869a-4578-89b4-bd1ee711fb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980874354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.980874354
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.20938351
Short name T898
Test name
Test status
Simulation time 945641109 ps
CPU time 4.62 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:11:53 PM PDT 24
Peak memory 224584 kb
Host smart-59eaa50a-533c-4d8e-8eb5-171392d51310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20938351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.20938351
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4121659214
Short name T393
Test name
Test status
Simulation time 3035174639 ps
CPU time 11.96 seconds
Started Jun 22 06:11:54 PM PDT 24
Finished Jun 22 06:12:06 PM PDT 24
Peak memory 221364 kb
Host smart-3fe9027e-e4fb-42f9-a33c-0b7431fbb52e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4121659214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4121659214
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2672455122
Short name T830
Test name
Test status
Simulation time 18984583914 ps
CPU time 23.26 seconds
Started Jun 22 06:11:49 PM PDT 24
Finished Jun 22 06:12:13 PM PDT 24
Peak memory 219612 kb
Host smart-f29cce2a-62bf-40d1-9fce-51ecfbb6259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672455122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2672455122
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2697205157
Short name T907
Test name
Test status
Simulation time 124396166 ps
CPU time 1.29 seconds
Started Jun 22 06:11:49 PM PDT 24
Finished Jun 22 06:11:51 PM PDT 24
Peak memory 208040 kb
Host smart-975bb6b5-18dd-4b69-b2b0-61e1da4c896f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697205157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2697205157
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3701035861
Short name T413
Test name
Test status
Simulation time 458707360 ps
CPU time 2.67 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:11:51 PM PDT 24
Peak memory 216448 kb
Host smart-0774b557-47f3-4697-a7f4-36a10da02df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701035861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3701035861
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1133823330
Short name T377
Test name
Test status
Simulation time 159141021 ps
CPU time 1.18 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:11:51 PM PDT 24
Peak memory 207120 kb
Host smart-4e632550-dacb-4930-baf4-b0b5d3d048aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133823330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1133823330
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1099805976
Short name T880
Test name
Test status
Simulation time 2545336144 ps
CPU time 2.89 seconds
Started Jun 22 06:11:48 PM PDT 24
Finished Jun 22 06:11:52 PM PDT 24
Peak memory 232996 kb
Host smart-29a8b0a1-1f20-4cd6-80cc-36f59764a150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099805976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1099805976
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1125113894
Short name T355
Test name
Test status
Simulation time 14794477 ps
CPU time 0.72 seconds
Started Jun 22 06:12:02 PM PDT 24
Finished Jun 22 06:12:04 PM PDT 24
Peak memory 205504 kb
Host smart-49d609fd-3014-4703-b6b8-0cbf2ea6edba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125113894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1125113894
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2680588896
Short name T874
Test name
Test status
Simulation time 249489252 ps
CPU time 2.81 seconds
Started Jun 22 06:11:59 PM PDT 24
Finished Jun 22 06:12:02 PM PDT 24
Peak memory 232868 kb
Host smart-6e68dc13-10ea-421c-87d2-bc7a64963f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680588896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2680588896
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1231780733
Short name T685
Test name
Test status
Simulation time 19654698 ps
CPU time 0.8 seconds
Started Jun 22 06:11:55 PM PDT 24
Finished Jun 22 06:11:57 PM PDT 24
Peak memory 206720 kb
Host smart-51274c3b-56a6-4b63-9c26-420bfadebc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231780733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1231780733
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3294584473
Short name T69
Test name
Test status
Simulation time 19743533469 ps
CPU time 131.34 seconds
Started Jun 22 06:11:56 PM PDT 24
Finished Jun 22 06:14:08 PM PDT 24
Peak memory 255796 kb
Host smart-9a07dc2e-4a05-406a-bb5a-9b4424205110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294584473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3294584473
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2471091727
Short name T787
Test name
Test status
Simulation time 35250990480 ps
CPU time 126.65 seconds
Started Jun 22 06:11:56 PM PDT 24
Finished Jun 22 06:14:03 PM PDT 24
Peak memory 256388 kb
Host smart-7fa99db0-7d6f-4b51-b346-e296bcf39ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471091727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2471091727
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.906389017
Short name T301
Test name
Test status
Simulation time 11157514618 ps
CPU time 184.71 seconds
Started Jun 22 06:11:56 PM PDT 24
Finished Jun 22 06:15:01 PM PDT 24
Peak memory 255536 kb
Host smart-c64d6ece-334c-4f37-bdea-f67a531c7e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906389017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.906389017
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.702079888
Short name T239
Test name
Test status
Simulation time 1222640788 ps
CPU time 22.48 seconds
Started Jun 22 06:11:53 PM PDT 24
Finished Jun 22 06:12:16 PM PDT 24
Peak memory 233908 kb
Host smart-e9afb36c-e48d-4f7d-9ffe-c785000e920a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702079888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.702079888
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1949123687
Short name T915
Test name
Test status
Simulation time 1102365791 ps
CPU time 9.55 seconds
Started Jun 22 06:11:59 PM PDT 24
Finished Jun 22 06:12:09 PM PDT 24
Peak memory 224572 kb
Host smart-62bba5e5-cec8-4a81-b985-44842689ad0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949123687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1949123687
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1946736061
Short name T600
Test name
Test status
Simulation time 44524674541 ps
CPU time 116.15 seconds
Started Jun 22 06:11:54 PM PDT 24
Finished Jun 22 06:13:51 PM PDT 24
Peak memory 234016 kb
Host smart-d9d08f0e-c27c-4a40-877e-50da70793858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946736061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1946736061
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.548003980
Short name T277
Test name
Test status
Simulation time 409472109 ps
CPU time 2.49 seconds
Started Jun 22 06:11:56 PM PDT 24
Finished Jun 22 06:11:59 PM PDT 24
Peak memory 224624 kb
Host smart-58b99005-da8a-4204-8db5-951e3f2520ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548003980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.548003980
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2618980971
Short name T684
Test name
Test status
Simulation time 41746045285 ps
CPU time 30.4 seconds
Started Jun 22 06:11:59 PM PDT 24
Finished Jun 22 06:12:30 PM PDT 24
Peak memory 224708 kb
Host smart-1240c5ae-14e7-4589-9a64-beddb324b54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618980971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2618980971
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.205430410
Short name T449
Test name
Test status
Simulation time 1687400592 ps
CPU time 10.57 seconds
Started Jun 22 06:11:59 PM PDT 24
Finished Jun 22 06:12:10 PM PDT 24
Peak memory 222184 kb
Host smart-f814a4ca-e09e-467a-8677-821f0818aecc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=205430410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.205430410
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2376430359
Short name T859
Test name
Test status
Simulation time 2250479970 ps
CPU time 25.33 seconds
Started Jun 22 06:11:54 PM PDT 24
Finished Jun 22 06:12:20 PM PDT 24
Peak memory 251192 kb
Host smart-12ac1c16-a91e-4517-93d8-2965d2ade764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376430359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2376430359
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1010458084
Short name T676
Test name
Test status
Simulation time 1234390205 ps
CPU time 4 seconds
Started Jun 22 06:11:54 PM PDT 24
Finished Jun 22 06:11:58 PM PDT 24
Peak memory 216400 kb
Host smart-78a25d0d-767a-4548-bb64-b71642df0e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010458084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1010458084
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1611390383
Short name T30
Test name
Test status
Simulation time 1394093443 ps
CPU time 1.17 seconds
Started Jun 22 06:11:55 PM PDT 24
Finished Jun 22 06:11:57 PM PDT 24
Peak memory 207192 kb
Host smart-27e78b85-d33f-4654-9ded-000be6569c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611390383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1611390383
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1023729499
Short name T455
Test name
Test status
Simulation time 1063906104 ps
CPU time 2.37 seconds
Started Jun 22 06:11:55 PM PDT 24
Finished Jun 22 06:11:58 PM PDT 24
Peak memory 216412 kb
Host smart-ed4dac6c-3f8b-4f09-aabb-ebb02b39874f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023729499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1023729499
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2041970717
Short name T743
Test name
Test status
Simulation time 29655655 ps
CPU time 0.69 seconds
Started Jun 22 06:11:56 PM PDT 24
Finished Jun 22 06:11:58 PM PDT 24
Peak memory 205700 kb
Host smart-75eb3725-728f-4b5b-95cf-170ee7ffe8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041970717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2041970717
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3912190035
Short name T954
Test name
Test status
Simulation time 3648058533 ps
CPU time 6.89 seconds
Started Jun 22 06:11:56 PM PDT 24
Finished Jun 22 06:12:04 PM PDT 24
Peak memory 224804 kb
Host smart-3debbe14-8cd5-4233-8762-a76a8bfa9afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912190035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3912190035
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2093289461
Short name T811
Test name
Test status
Simulation time 37251264 ps
CPU time 0.7 seconds
Started Jun 22 06:12:02 PM PDT 24
Finished Jun 22 06:12:03 PM PDT 24
Peak memory 205852 kb
Host smart-2bd4ada5-7788-4db9-8dc3-54f97861febe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093289461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2093289461
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.55171223
Short name T786
Test name
Test status
Simulation time 1654116378 ps
CPU time 15.81 seconds
Started Jun 22 06:12:00 PM PDT 24
Finished Jun 22 06:12:16 PM PDT 24
Peak memory 232872 kb
Host smart-e961487e-85f4-4abc-b864-a17192584008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55171223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.55171223
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1103694119
Short name T861
Test name
Test status
Simulation time 87458215 ps
CPU time 0.78 seconds
Started Jun 22 06:12:03 PM PDT 24
Finished Jun 22 06:12:05 PM PDT 24
Peak memory 207080 kb
Host smart-36c93de8-3b05-4e4b-9583-945bf1d5aaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103694119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1103694119
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1015508221
Short name T178
Test name
Test status
Simulation time 19299846513 ps
CPU time 37.01 seconds
Started Jun 22 06:12:02 PM PDT 24
Finished Jun 22 06:12:40 PM PDT 24
Peak memory 249404 kb
Host smart-244f3024-34a4-42ea-bc3e-2d49909b60cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015508221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1015508221
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3404023262
Short name T330
Test name
Test status
Simulation time 6217350953 ps
CPU time 26.23 seconds
Started Jun 22 06:12:05 PM PDT 24
Finished Jun 22 06:12:32 PM PDT 24
Peak memory 217700 kb
Host smart-1cc60c96-5376-47cc-b5b4-0fb0e6e1ab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404023262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3404023262
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2137095787
Short name T923
Test name
Test status
Simulation time 92840498769 ps
CPU time 208.66 seconds
Started Jun 22 06:12:10 PM PDT 24
Finished Jun 22 06:15:40 PM PDT 24
Peak memory 240668 kb
Host smart-8626b78a-80b6-421d-9396-4eb711a5ed5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137095787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2137095787
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1234509818
Short name T499
Test name
Test status
Simulation time 97037121 ps
CPU time 3.67 seconds
Started Jun 22 06:12:04 PM PDT 24
Finished Jun 22 06:12:09 PM PDT 24
Peak memory 232876 kb
Host smart-f8fac164-4b1e-42fa-b127-5affcd3993bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234509818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1234509818
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2947821797
Short name T394
Test name
Test status
Simulation time 246921255 ps
CPU time 4.24 seconds
Started Jun 22 06:12:03 PM PDT 24
Finished Jun 22 06:12:08 PM PDT 24
Peak memory 224604 kb
Host smart-3840c9b7-fe6f-45e5-8062-f131146c7816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947821797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2947821797
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2163962077
Short name T819
Test name
Test status
Simulation time 1301649280 ps
CPU time 14.01 seconds
Started Jun 22 06:12:10 PM PDT 24
Finished Jun 22 06:12:25 PM PDT 24
Peak memory 249260 kb
Host smart-02d9e718-123f-4d3a-8330-4f60e56c2594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163962077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2163962077
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2229881512
Short name T952
Test name
Test status
Simulation time 197480889 ps
CPU time 2.85 seconds
Started Jun 22 06:12:10 PM PDT 24
Finished Jun 22 06:12:14 PM PDT 24
Peak memory 232840 kb
Host smart-a545823c-16bd-4b29-8d40-e16020d5a87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229881512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2229881512
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.548933095
Short name T628
Test name
Test status
Simulation time 2137420794 ps
CPU time 6.15 seconds
Started Jun 22 06:12:01 PM PDT 24
Finished Jun 22 06:12:08 PM PDT 24
Peak memory 224700 kb
Host smart-39e6afb1-c805-4878-b211-5b02c0e154b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548933095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.548933095
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2988970260
Short name T921
Test name
Test status
Simulation time 3745781687 ps
CPU time 6.92 seconds
Started Jun 22 06:12:04 PM PDT 24
Finished Jun 22 06:12:12 PM PDT 24
Peak memory 223628 kb
Host smart-d173d264-fe34-490b-8637-7f025d64a82a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2988970260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2988970260
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.53943745
Short name T689
Test name
Test status
Simulation time 5993455955 ps
CPU time 71.24 seconds
Started Jun 22 06:12:03 PM PDT 24
Finished Jun 22 06:13:15 PM PDT 24
Peak memory 249792 kb
Host smart-58517bb1-c9af-4827-a9ad-9aabc74de0d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53943745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress
_all.53943745
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.68107353
Short name T169
Test name
Test status
Simulation time 18611678 ps
CPU time 0.79 seconds
Started Jun 22 06:12:02 PM PDT 24
Finished Jun 22 06:12:04 PM PDT 24
Peak memory 205796 kb
Host smart-b4fffa80-3804-4d66-af59-66929c795930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68107353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.68107353
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1989879341
Short name T696
Test name
Test status
Simulation time 8402344435 ps
CPU time 19.55 seconds
Started Jun 22 06:12:02 PM PDT 24
Finished Jun 22 06:12:23 PM PDT 24
Peak memory 216488 kb
Host smart-dae62447-28e3-4d9b-9018-f138fbab4824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989879341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1989879341
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3612044769
Short name T860
Test name
Test status
Simulation time 17852430 ps
CPU time 1.11 seconds
Started Jun 22 06:12:03 PM PDT 24
Finished Jun 22 06:12:05 PM PDT 24
Peak memory 207504 kb
Host smart-19d2daf3-9bb7-4aef-9bb6-19aa548fdc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612044769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3612044769
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.631729331
Short name T371
Test name
Test status
Simulation time 18472605 ps
CPU time 0.74 seconds
Started Jun 22 06:12:04 PM PDT 24
Finished Jun 22 06:12:05 PM PDT 24
Peak memory 206096 kb
Host smart-bbc770d3-9608-4b2b-849d-3cfd59ebe826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631729331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.631729331
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3629338036
Short name T104
Test name
Test status
Simulation time 118442330 ps
CPU time 2.39 seconds
Started Jun 22 06:12:04 PM PDT 24
Finished Jun 22 06:12:07 PM PDT 24
Peak memory 224372 kb
Host smart-b42f0ecf-65f7-419b-a4d4-674462733850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629338036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3629338036
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.112136773
Short name T22
Test name
Test status
Simulation time 76355274 ps
CPU time 0.73 seconds
Started Jun 22 06:12:07 PM PDT 24
Finished Jun 22 06:12:09 PM PDT 24
Peak memory 204936 kb
Host smart-23bf30f9-66b0-4641-a097-a12ec22addf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112136773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.112136773
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4168887731
Short name T882
Test name
Test status
Simulation time 4478634911 ps
CPU time 6.79 seconds
Started Jun 22 06:12:00 PM PDT 24
Finished Jun 22 06:12:08 PM PDT 24
Peak memory 233000 kb
Host smart-72b0b322-47a7-46bf-8c3d-bca6eae747a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168887731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4168887731
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4022814073
Short name T514
Test name
Test status
Simulation time 13530104 ps
CPU time 0.78 seconds
Started Jun 22 06:12:04 PM PDT 24
Finished Jun 22 06:12:06 PM PDT 24
Peak memory 206732 kb
Host smart-6a83c72a-865f-426b-aaf4-6197b5dbd5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022814073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4022814073
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.864778034
Short name T741
Test name
Test status
Simulation time 3397820005 ps
CPU time 30.61 seconds
Started Jun 22 06:12:10 PM PDT 24
Finished Jun 22 06:12:41 PM PDT 24
Peak memory 224852 kb
Host smart-1403c216-1853-49eb-8927-a30f645dff03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864778034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.864778034
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2976624690
Short name T337
Test name
Test status
Simulation time 35302282941 ps
CPU time 402.15 seconds
Started Jun 22 06:12:10 PM PDT 24
Finished Jun 22 06:18:54 PM PDT 24
Peak memory 266808 kb
Host smart-71eeb229-d36b-4f7e-8bc8-15ecfdc78596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976624690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2976624690
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1738015300
Short name T26
Test name
Test status
Simulation time 316545963 ps
CPU time 3.95 seconds
Started Jun 22 06:12:01 PM PDT 24
Finished Jun 22 06:12:05 PM PDT 24
Peak memory 233244 kb
Host smart-b85edc38-96cb-4868-ad57-3d5a53725152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738015300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1738015300
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.399696408
Short name T908
Test name
Test status
Simulation time 4270040766 ps
CPU time 8.21 seconds
Started Jun 22 06:12:01 PM PDT 24
Finished Jun 22 06:12:10 PM PDT 24
Peak memory 232944 kb
Host smart-90772a19-3c80-4452-9998-a9a7df8b6567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399696408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.399696408
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1200364379
Short name T610
Test name
Test status
Simulation time 604220961 ps
CPU time 6.41 seconds
Started Jun 22 06:12:03 PM PDT 24
Finished Jun 22 06:12:10 PM PDT 24
Peak memory 224640 kb
Host smart-7852517d-aef2-4f31-8528-8ef12791e888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200364379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1200364379
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.697000633
Short name T220
Test name
Test status
Simulation time 1342191501 ps
CPU time 6.36 seconds
Started Jun 22 06:12:02 PM PDT 24
Finished Jun 22 06:12:09 PM PDT 24
Peak memory 240764 kb
Host smart-c513fe9e-86f0-4af2-8b27-9ad0db5e79db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697000633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.697000633
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1625059314
Short name T213
Test name
Test status
Simulation time 556274152 ps
CPU time 5.67 seconds
Started Jun 22 06:12:03 PM PDT 24
Finished Jun 22 06:12:09 PM PDT 24
Peak memory 224684 kb
Host smart-9484a8a1-efc9-45f2-915a-98dd61f06cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625059314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1625059314
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3710639263
Short name T154
Test name
Test status
Simulation time 255740475 ps
CPU time 3.48 seconds
Started Jun 22 06:12:03 PM PDT 24
Finished Jun 22 06:12:07 PM PDT 24
Peak memory 220740 kb
Host smart-3851fc9c-daf3-4c1c-a96a-3ccca4185ae2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3710639263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3710639263
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.281681050
Short name T16
Test name
Test status
Simulation time 398880011 ps
CPU time 0.94 seconds
Started Jun 22 06:12:10 PM PDT 24
Finished Jun 22 06:12:11 PM PDT 24
Peak memory 206928 kb
Host smart-dabae432-df2a-48bf-8ece-0448b93e3ecb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281681050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.281681050
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2787218815
Short name T832
Test name
Test status
Simulation time 5550605303 ps
CPU time 7.41 seconds
Started Jun 22 06:12:03 PM PDT 24
Finished Jun 22 06:12:11 PM PDT 24
Peak memory 216836 kb
Host smart-71dd0cc1-7f00-4b5a-9c52-0029c6fe6400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787218815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2787218815
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3447394735
Short name T935
Test name
Test status
Simulation time 616750529 ps
CPU time 4.02 seconds
Started Jun 22 06:12:11 PM PDT 24
Finished Jun 22 06:12:16 PM PDT 24
Peak memory 216444 kb
Host smart-9de1c58f-b011-441a-9d62-d30b2a433e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447394735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3447394735
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4164230297
Short name T347
Test name
Test status
Simulation time 27008838 ps
CPU time 1.1 seconds
Started Jun 22 06:12:02 PM PDT 24
Finished Jun 22 06:12:03 PM PDT 24
Peak memory 207784 kb
Host smart-fe2ff489-6995-4b9c-a9a8-2eddcaadc51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164230297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4164230297
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4034167015
Short name T479
Test name
Test status
Simulation time 89303865 ps
CPU time 0.9 seconds
Started Jun 22 06:12:01 PM PDT 24
Finished Jun 22 06:12:02 PM PDT 24
Peak memory 206104 kb
Host smart-e32e6082-52b9-4f62-a50d-95e785f0d9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034167015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4034167015
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3409043653
Short name T545
Test name
Test status
Simulation time 9700906029 ps
CPU time 21.42 seconds
Started Jun 22 06:12:02 PM PDT 24
Finished Jun 22 06:12:24 PM PDT 24
Peak memory 233020 kb
Host smart-3cbe1289-b5ba-4f59-b974-c958b2531df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409043653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3409043653
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2741413658
Short name T731
Test name
Test status
Simulation time 31291565 ps
CPU time 0.71 seconds
Started Jun 22 06:12:06 PM PDT 24
Finished Jun 22 06:12:08 PM PDT 24
Peak memory 204884 kb
Host smart-a753f415-3d3e-4086-be5a-257843a65b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741413658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2741413658
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1883960335
Short name T828
Test name
Test status
Simulation time 277352503 ps
CPU time 6.15 seconds
Started Jun 22 06:12:11 PM PDT 24
Finished Jun 22 06:12:18 PM PDT 24
Peak memory 232860 kb
Host smart-e7beb040-9712-4b00-89c7-81d619062607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883960335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1883960335
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.930279004
Short name T938
Test name
Test status
Simulation time 20188582 ps
CPU time 0.81 seconds
Started Jun 22 06:12:11 PM PDT 24
Finished Jun 22 06:12:12 PM PDT 24
Peak memory 206680 kb
Host smart-308d4b43-8f7e-49e9-9f8a-cef1fb9b5d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930279004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.930279004
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3561285485
Short name T927
Test name
Test status
Simulation time 11486079258 ps
CPU time 41.41 seconds
Started Jun 22 06:12:09 PM PDT 24
Finished Jun 22 06:12:51 PM PDT 24
Peak memory 239084 kb
Host smart-bc0c149c-1149-482a-8c2f-3df250e1c1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561285485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3561285485
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2462279445
Short name T62
Test name
Test status
Simulation time 6279237150 ps
CPU time 124.83 seconds
Started Jun 22 06:12:11 PM PDT 24
Finished Jun 22 06:14:16 PM PDT 24
Peak memory 252924 kb
Host smart-e744ca09-e6e7-41ff-9605-f2e2e278b59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462279445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2462279445
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2324123162
Short name T229
Test name
Test status
Simulation time 144342222321 ps
CPU time 265.73 seconds
Started Jun 22 06:12:12 PM PDT 24
Finished Jun 22 06:16:38 PM PDT 24
Peak memory 265760 kb
Host smart-15fcec15-26d6-4de6-95bd-d17c50235326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324123162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2324123162
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.979538771
Short name T490
Test name
Test status
Simulation time 235882994 ps
CPU time 4.4 seconds
Started Jun 22 06:12:11 PM PDT 24
Finished Jun 22 06:12:17 PM PDT 24
Peak memory 232888 kb
Host smart-3dec7d37-6357-4d15-9b3f-d679c90cb985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979538771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.979538771
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1077951594
Short name T649
Test name
Test status
Simulation time 1045017058 ps
CPU time 12.65 seconds
Started Jun 22 06:12:08 PM PDT 24
Finished Jun 22 06:12:21 PM PDT 24
Peak memory 232872 kb
Host smart-bd1b2c18-9ed6-4951-bdd9-03517312226f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077951594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1077951594
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.895498708
Short name T746
Test name
Test status
Simulation time 3316532746 ps
CPU time 12.15 seconds
Started Jun 22 06:12:12 PM PDT 24
Finished Jun 22 06:12:25 PM PDT 24
Peak memory 224772 kb
Host smart-c0697915-b80f-4525-bd18-eb32b7f5321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895498708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.895498708
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1981066965
Short name T232
Test name
Test status
Simulation time 2813931785 ps
CPU time 9.12 seconds
Started Jun 22 06:12:08 PM PDT 24
Finished Jun 22 06:12:18 PM PDT 24
Peak memory 240956 kb
Host smart-12af24f9-3484-4c2e-b2c4-ff992f0c1403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981066965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1981066965
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3335132710
Short name T962
Test name
Test status
Simulation time 3365791070 ps
CPU time 5.59 seconds
Started Jun 22 06:12:13 PM PDT 24
Finished Jun 22 06:12:19 PM PDT 24
Peak memory 233024 kb
Host smart-9581a2ba-ab17-4ed1-93e0-5862af00e16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335132710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3335132710
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3179552962
Short name T408
Test name
Test status
Simulation time 2800841237 ps
CPU time 8.08 seconds
Started Jun 22 06:12:11 PM PDT 24
Finished Jun 22 06:12:20 PM PDT 24
Peak memory 223304 kb
Host smart-273f88c2-e77f-4cee-887d-dd3eee15eb1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3179552962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3179552962
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3255973588
Short name T865
Test name
Test status
Simulation time 142483014093 ps
CPU time 318.92 seconds
Started Jun 22 06:12:10 PM PDT 24
Finished Jun 22 06:17:29 PM PDT 24
Peak memory 255060 kb
Host smart-d4491e91-7003-4a41-9085-cd1d446d0a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255973588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3255973588
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3429156810
Short name T742
Test name
Test status
Simulation time 1941847730 ps
CPU time 10.75 seconds
Started Jun 22 06:12:19 PM PDT 24
Finished Jun 22 06:12:30 PM PDT 24
Peak memory 216452 kb
Host smart-c25e876d-af0b-4e2c-a0e4-c006ecf8638b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429156810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3429156810
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1993522808
Short name T905
Test name
Test status
Simulation time 64201818431 ps
CPU time 17.22 seconds
Started Jun 22 06:12:10 PM PDT 24
Finished Jun 22 06:12:28 PM PDT 24
Peak memory 216612 kb
Host smart-b014f1a0-7545-4c12-8333-db0d3192ba54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993522808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1993522808
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4290519402
Short name T673
Test name
Test status
Simulation time 42641675 ps
CPU time 0.69 seconds
Started Jun 22 06:12:10 PM PDT 24
Finished Jun 22 06:12:11 PM PDT 24
Peak memory 205728 kb
Host smart-b24e248d-bb8c-4a8a-b52a-f1f59031e124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290519402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4290519402
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4190013424
Short name T609
Test name
Test status
Simulation time 79325570 ps
CPU time 0.83 seconds
Started Jun 22 06:12:08 PM PDT 24
Finished Jun 22 06:12:09 PM PDT 24
Peak memory 206088 kb
Host smart-7a3660e0-36ef-4ca2-b558-182e8a7180c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190013424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4190013424
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3298885722
Short name T749
Test name
Test status
Simulation time 5429954682 ps
CPU time 17.26 seconds
Started Jun 22 06:12:11 PM PDT 24
Finished Jun 22 06:12:29 PM PDT 24
Peak memory 233020 kb
Host smart-eab76948-29a1-476e-b071-6c1af292da3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298885722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3298885722
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1737101831
Short name T826
Test name
Test status
Simulation time 28401715 ps
CPU time 0.7 seconds
Started Jun 22 06:12:11 PM PDT 24
Finished Jun 22 06:12:13 PM PDT 24
Peak memory 204936 kb
Host smart-4a2f3736-4968-4079-911d-ab1cca75f12b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737101831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1737101831
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2693915136
Short name T274
Test name
Test status
Simulation time 243826881 ps
CPU time 3.79 seconds
Started Jun 22 06:12:13 PM PDT 24
Finished Jun 22 06:12:17 PM PDT 24
Peak memory 224636 kb
Host smart-60276c3d-f493-4990-bb65-885d0b8e32fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693915136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2693915136
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3056355541
Short name T648
Test name
Test status
Simulation time 19054280 ps
CPU time 0.75 seconds
Started Jun 22 06:12:09 PM PDT 24
Finished Jun 22 06:12:10 PM PDT 24
Peak memory 207064 kb
Host smart-eb167845-9ac6-4217-ba48-b1f68ad08848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056355541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3056355541
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.161524375
Short name T296
Test name
Test status
Simulation time 5480944564 ps
CPU time 64.9 seconds
Started Jun 22 06:12:08 PM PDT 24
Finished Jun 22 06:13:14 PM PDT 24
Peak memory 266296 kb
Host smart-3c2b63c6-2bb4-4a15-8d2e-73aa9d890268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161524375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.161524375
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2250930073
Short name T42
Test name
Test status
Simulation time 23824348038 ps
CPU time 98.59 seconds
Started Jun 22 06:12:12 PM PDT 24
Finished Jun 22 06:13:51 PM PDT 24
Peak memory 250668 kb
Host smart-cabab5c6-fa22-4bf1-a622-0a9e83024d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250930073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2250930073
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.200115614
Short name T41
Test name
Test status
Simulation time 3328255616 ps
CPU time 25.57 seconds
Started Jun 22 06:12:19 PM PDT 24
Finished Jun 22 06:12:45 PM PDT 24
Peak memory 241236 kb
Host smart-800fd6f5-6f96-4e13-8ee1-567ad55e4c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200115614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.200115614
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3702607389
Short name T319
Test name
Test status
Simulation time 10164581121 ps
CPU time 45.63 seconds
Started Jun 22 06:12:12 PM PDT 24
Finished Jun 22 06:12:58 PM PDT 24
Peak memory 252052 kb
Host smart-5bbc4793-664b-45aa-892d-de4081e20736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702607389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3702607389
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1856695332
Short name T834
Test name
Test status
Simulation time 157603148 ps
CPU time 4.19 seconds
Started Jun 22 06:12:12 PM PDT 24
Finished Jun 22 06:12:17 PM PDT 24
Peak memory 232820 kb
Host smart-a1f23483-14b3-42aa-89d6-398a98559502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856695332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1856695332
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.20084186
Short name T240
Test name
Test status
Simulation time 2737394231 ps
CPU time 9.21 seconds
Started Jun 22 06:12:11 PM PDT 24
Finished Jun 22 06:12:21 PM PDT 24
Peak memory 224744 kb
Host smart-84aedd19-76e0-4e14-bbbd-dac47fadd50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20084186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.20084186
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.240557107
Short name T807
Test name
Test status
Simulation time 50062166022 ps
CPU time 22.02 seconds
Started Jun 22 06:12:11 PM PDT 24
Finished Jun 22 06:12:34 PM PDT 24
Peak memory 232996 kb
Host smart-450aa6f8-d731-4b29-b0f1-a58d6da91c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240557107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.240557107
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3561885821
Short name T548
Test name
Test status
Simulation time 47825372886 ps
CPU time 16.86 seconds
Started Jun 22 06:12:07 PM PDT 24
Finished Jun 22 06:12:25 PM PDT 24
Peak memory 233020 kb
Host smart-2a0b8858-263d-4eb7-868d-f153fcc25f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561885821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3561885821
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.763148216
Short name T579
Test name
Test status
Simulation time 91626118 ps
CPU time 3.71 seconds
Started Jun 22 06:12:11 PM PDT 24
Finished Jun 22 06:12:15 PM PDT 24
Peak memory 223580 kb
Host smart-56541f42-95b1-494c-87bf-321b701e93b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=763148216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.763148216
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2179746253
Short name T719
Test name
Test status
Simulation time 4846963150 ps
CPU time 119.57 seconds
Started Jun 22 06:12:18 PM PDT 24
Finished Jun 22 06:14:19 PM PDT 24
Peak memory 273704 kb
Host smart-32ba7e25-0106-40d9-b989-0d3588db3c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179746253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2179746253
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1887065725
Short name T651
Test name
Test status
Simulation time 25431564482 ps
CPU time 34.13 seconds
Started Jun 22 06:12:19 PM PDT 24
Finished Jun 22 06:12:54 PM PDT 24
Peak memory 220384 kb
Host smart-5a780776-308c-4ae8-a8f4-1f9941de7248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887065725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1887065725
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3755077325
Short name T581
Test name
Test status
Simulation time 7640626298 ps
CPU time 13.5 seconds
Started Jun 22 06:12:09 PM PDT 24
Finished Jun 22 06:12:23 PM PDT 24
Peak memory 216520 kb
Host smart-43a8e8e1-7a65-4c08-ab45-60015274b854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755077325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3755077325
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.119714680
Short name T636
Test name
Test status
Simulation time 57489809 ps
CPU time 0.71 seconds
Started Jun 22 06:12:10 PM PDT 24
Finished Jun 22 06:12:12 PM PDT 24
Peak memory 205656 kb
Host smart-9f1b10a7-9583-4131-aa74-0af0102739cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119714680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.119714680
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3183892080
Short name T736
Test name
Test status
Simulation time 138850892 ps
CPU time 0.75 seconds
Started Jun 22 06:12:12 PM PDT 24
Finished Jun 22 06:12:13 PM PDT 24
Peak memory 206076 kb
Host smart-592ca010-f2bb-41c9-b23f-a6f16858f1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183892080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3183892080
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3601845836
Short name T444
Test name
Test status
Simulation time 427287110 ps
CPU time 3.54 seconds
Started Jun 22 06:12:12 PM PDT 24
Finished Jun 22 06:12:16 PM PDT 24
Peak memory 224856 kb
Host smart-ad8cdb61-97ff-46ec-bc2c-e03e5bf1069e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601845836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3601845836
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3348835230
Short name T824
Test name
Test status
Simulation time 12381008 ps
CPU time 0.73 seconds
Started Jun 22 06:12:29 PM PDT 24
Finished Jun 22 06:12:31 PM PDT 24
Peak memory 205516 kb
Host smart-49ecc2d7-af30-4609-8506-ed2dc3224b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348835230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3348835230
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1108981804
Short name T93
Test name
Test status
Simulation time 261209183 ps
CPU time 3.41 seconds
Started Jun 22 06:12:21 PM PDT 24
Finished Jun 22 06:12:24 PM PDT 24
Peak memory 232812 kb
Host smart-7b8423ea-5db6-45b3-a418-10c950ec27d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108981804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1108981804
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3324345382
Short name T4
Test name
Test status
Simulation time 31971329 ps
CPU time 0.81 seconds
Started Jun 22 06:12:18 PM PDT 24
Finished Jun 22 06:12:20 PM PDT 24
Peak memory 205724 kb
Host smart-948c4b7d-ab40-488f-99ea-62bc2f0ea9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324345382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3324345382
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3699176901
Short name T302
Test name
Test status
Simulation time 7414419356 ps
CPU time 40.02 seconds
Started Jun 22 06:12:19 PM PDT 24
Finished Jun 22 06:12:59 PM PDT 24
Peak memory 238632 kb
Host smart-99528bb3-dc90-4c90-ac8d-9448dbd18f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699176901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3699176901
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2609288297
Short name T604
Test name
Test status
Simulation time 194967110155 ps
CPU time 248.48 seconds
Started Jun 22 06:12:19 PM PDT 24
Finished Jun 22 06:16:28 PM PDT 24
Peak memory 249440 kb
Host smart-593c9564-6e2b-4145-98c6-a790bde6b070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609288297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2609288297
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.890955502
Short name T32
Test name
Test status
Simulation time 85801911340 ps
CPU time 199.9 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:15:49 PM PDT 24
Peak memory 256584 kb
Host smart-de4489ed-6417-4cc8-9d01-972e6dea0372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890955502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.890955502
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1162469428
Short name T667
Test name
Test status
Simulation time 406070921 ps
CPU time 6.43 seconds
Started Jun 22 06:12:20 PM PDT 24
Finished Jun 22 06:12:27 PM PDT 24
Peak memory 233924 kb
Host smart-8001461c-9625-4b8e-8118-b19ea22f9fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162469428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1162469428
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1207111217
Short name T668
Test name
Test status
Simulation time 1965742739 ps
CPU time 7 seconds
Started Jun 22 06:12:18 PM PDT 24
Finished Jun 22 06:12:25 PM PDT 24
Peak memory 232892 kb
Host smart-bd90b262-2cc4-4fa9-a56b-891b344797c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207111217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1207111217
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2325004133
Short name T559
Test name
Test status
Simulation time 317715537 ps
CPU time 3.54 seconds
Started Jun 22 06:12:20 PM PDT 24
Finished Jun 22 06:12:24 PM PDT 24
Peak memory 224648 kb
Host smart-568b268c-6bed-4d73-8aa5-168f231c1b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325004133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2325004133
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.365246322
Short name T679
Test name
Test status
Simulation time 1559428088 ps
CPU time 5.98 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:12:35 PM PDT 24
Peak memory 240624 kb
Host smart-a9cb8392-27ce-4d05-9794-25fce16bc350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365246322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.365246322
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.808218510
Short name T531
Test name
Test status
Simulation time 7701155665 ps
CPU time 13.94 seconds
Started Jun 22 06:12:29 PM PDT 24
Finished Jun 22 06:12:44 PM PDT 24
Peak memory 234048 kb
Host smart-9ab47988-66ff-44cd-91a6-e38b5f01aa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808218510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.808218510
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2574812954
Short name T396
Test name
Test status
Simulation time 1029742924 ps
CPU time 4.45 seconds
Started Jun 22 06:12:20 PM PDT 24
Finished Jun 22 06:12:25 PM PDT 24
Peak memory 222732 kb
Host smart-10779317-02e2-4342-859c-1fe172e83dc7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2574812954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2574812954
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2857562736
Short name T540
Test name
Test status
Simulation time 212157790453 ps
CPU time 234.24 seconds
Started Jun 22 06:12:19 PM PDT 24
Finished Jun 22 06:16:14 PM PDT 24
Peak memory 249448 kb
Host smart-f3b6befa-1ff6-4c0d-a633-e708da40778f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857562736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2857562736
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2656852221
Short name T810
Test name
Test status
Simulation time 3354453703 ps
CPU time 21.42 seconds
Started Jun 22 06:12:18 PM PDT 24
Finished Jun 22 06:12:40 PM PDT 24
Peak memory 216556 kb
Host smart-1e3d9e86-4ebe-425f-8cd5-1cebbeca7f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656852221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2656852221
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3128681335
Short name T947
Test name
Test status
Simulation time 3251174494 ps
CPU time 7.41 seconds
Started Jun 22 06:12:18 PM PDT 24
Finished Jun 22 06:12:26 PM PDT 24
Peak memory 216520 kb
Host smart-e85e0974-656a-42f5-a29d-2b06e2b6aa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128681335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3128681335
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.50503908
Short name T59
Test name
Test status
Simulation time 179227260 ps
CPU time 1.11 seconds
Started Jun 22 06:12:20 PM PDT 24
Finished Jun 22 06:12:22 PM PDT 24
Peak memory 207708 kb
Host smart-ce483aa1-3d66-46bf-9c44-3bb9628a2bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50503908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.50503908
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.137496160
Short name T494
Test name
Test status
Simulation time 23493361 ps
CPU time 0.71 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:28 PM PDT 24
Peak memory 206096 kb
Host smart-61dec3ab-1ec9-41c9-89e6-744e895f048b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137496160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.137496160
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2629095999
Short name T805
Test name
Test status
Simulation time 11514918231 ps
CPU time 10.19 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:12:39 PM PDT 24
Peak memory 224684 kb
Host smart-d5ee14fc-6702-47fb-be34-bc32315d5032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629095999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2629095999
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4253402578
Short name T570
Test name
Test status
Simulation time 11860605 ps
CPU time 0.74 seconds
Started Jun 22 06:12:28 PM PDT 24
Finished Jun 22 06:12:30 PM PDT 24
Peak memory 205460 kb
Host smart-fd928728-ea1e-44e9-b009-e95b1545df9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253402578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4253402578
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1651666011
Short name T611
Test name
Test status
Simulation time 596287490 ps
CPU time 7.27 seconds
Started Jun 22 06:12:28 PM PDT 24
Finished Jun 22 06:12:37 PM PDT 24
Peak memory 224648 kb
Host smart-218a852e-2be4-4bcf-ab59-e51c7757b7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651666011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1651666011
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2476101403
Short name T140
Test name
Test status
Simulation time 147606769 ps
CPU time 0.78 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:12:30 PM PDT 24
Peak memory 206700 kb
Host smart-531beda2-d07d-4139-8ed4-0c99aad81f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476101403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2476101403
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.356169276
Short name T674
Test name
Test status
Simulation time 499856635 ps
CPU time 12.2 seconds
Started Jun 22 06:12:28 PM PDT 24
Finished Jun 22 06:12:42 PM PDT 24
Peak memory 235632 kb
Host smart-ebbeee3e-e5c6-414f-a9d0-432fe2e07b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356169276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.356169276
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3384733814
Short name T914
Test name
Test status
Simulation time 84123574695 ps
CPU time 79.1 seconds
Started Jun 22 06:12:32 PM PDT 24
Finished Jun 22 06:13:52 PM PDT 24
Peak memory 249604 kb
Host smart-3e8432d8-3af0-41b0-86bd-d3bbb98c564d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384733814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3384733814
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.142297661
Short name T328
Test name
Test status
Simulation time 1526658164 ps
CPU time 12.53 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:12:41 PM PDT 24
Peak memory 217556 kb
Host smart-90d831c5-2216-4f4f-a8ba-6f985795e17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142297661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.142297661
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1724354813
Short name T308
Test name
Test status
Simulation time 297784917 ps
CPU time 9.1 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:35 PM PDT 24
Peak memory 232856 kb
Host smart-ca3cb0ae-5995-4b86-a553-e95bd3842c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724354813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1724354813
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.188386828
Short name T846
Test name
Test status
Simulation time 2415997723 ps
CPU time 8.11 seconds
Started Jun 22 06:12:28 PM PDT 24
Finished Jun 22 06:12:38 PM PDT 24
Peak memory 224952 kb
Host smart-e7c181d5-448a-48fd-8741-abf22783a674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188386828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.188386828
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.697979705
Short name T461
Test name
Test status
Simulation time 72322451 ps
CPU time 2.18 seconds
Started Jun 22 06:12:24 PM PDT 24
Finished Jun 22 06:12:27 PM PDT 24
Peak memory 224280 kb
Host smart-0e324136-2f33-4857-a584-deb847ededec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697979705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.697979705
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4238028326
Short name T693
Test name
Test status
Simulation time 166774827 ps
CPU time 2.73 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:12:32 PM PDT 24
Peak memory 232868 kb
Host smart-d2909998-6a91-459c-9550-6c3e31b3bbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238028326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4238028326
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4040589224
Short name T6
Test name
Test status
Simulation time 4714189974 ps
CPU time 10.31 seconds
Started Jun 22 06:12:21 PM PDT 24
Finished Jun 22 06:12:31 PM PDT 24
Peak memory 233016 kb
Host smart-13068b5c-d532-47e1-b702-9a4664376842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040589224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4040589224
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3596112158
Short name T825
Test name
Test status
Simulation time 1584745249 ps
CPU time 8.99 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:37 PM PDT 24
Peak memory 223160 kb
Host smart-5584aa33-f53e-4579-a19d-674e27fb090b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3596112158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3596112158
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1098976708
Short name T15
Test name
Test status
Simulation time 23042029278 ps
CPU time 62.21 seconds
Started Jun 22 06:12:28 PM PDT 24
Finished Jun 22 06:13:32 PM PDT 24
Peak memory 233004 kb
Host smart-c1cf0a9e-96bd-4c1f-918c-e7a2502447fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098976708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1098976708
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1156621851
Short name T529
Test name
Test status
Simulation time 6031710552 ps
CPU time 34.01 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:13:02 PM PDT 24
Peak memory 216576 kb
Host smart-ee8b8ab4-3014-4607-a795-c9b201f802d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156621851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1156621851
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2623423934
Short name T533
Test name
Test status
Simulation time 10185746079 ps
CPU time 29.9 seconds
Started Jun 22 06:12:17 PM PDT 24
Finished Jun 22 06:12:47 PM PDT 24
Peak memory 216540 kb
Host smart-4ff0f174-248e-487e-ab6a-01356b0942c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623423934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2623423934
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1741812960
Short name T397
Test name
Test status
Simulation time 16677672 ps
CPU time 0.68 seconds
Started Jun 22 06:12:29 PM PDT 24
Finished Jun 22 06:12:31 PM PDT 24
Peak memory 205728 kb
Host smart-d0a88322-5590-49f9-a5a9-9b0393f8d653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741812960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1741812960
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1434519127
Short name T167
Test name
Test status
Simulation time 71812586 ps
CPU time 0.8 seconds
Started Jun 22 06:12:15 PM PDT 24
Finished Jun 22 06:12:16 PM PDT 24
Peak memory 206104 kb
Host smart-03704085-b4c1-428f-ab67-34a4a871af8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434519127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1434519127
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3156705555
Short name T940
Test name
Test status
Simulation time 2752843637 ps
CPU time 7.72 seconds
Started Jun 22 06:12:28 PM PDT 24
Finished Jun 22 06:12:38 PM PDT 24
Peak memory 224816 kb
Host smart-1abb3b45-8d70-4944-af3b-d6680c45a6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156705555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3156705555
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2746511663
Short name T442
Test name
Test status
Simulation time 65580021 ps
CPU time 0.71 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:12:29 PM PDT 24
Peak memory 205540 kb
Host smart-3cb4be4b-7ec6-4177-b015-5de436735fb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746511663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2746511663
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.538937785
Short name T474
Test name
Test status
Simulation time 284381008 ps
CPU time 4.25 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:12:33 PM PDT 24
Peak memory 232872 kb
Host smart-9b64d415-cfa5-48d1-9adc-b2b89d6a1608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538937785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.538937785
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.4005156179
Short name T701
Test name
Test status
Simulation time 182531848 ps
CPU time 0.77 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:12:30 PM PDT 24
Peak memory 207020 kb
Host smart-95e4b428-e0fe-40ce-ac38-3ebb7a3c65e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005156179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.4005156179
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3593919600
Short name T205
Test name
Test status
Simulation time 781935198 ps
CPU time 16.12 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:43 PM PDT 24
Peak memory 250236 kb
Host smart-bd53209e-5a77-428f-be34-49e268d7f9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593919600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3593919600
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1038362853
Short name T236
Test name
Test status
Simulation time 18278460221 ps
CPU time 176.42 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:15:26 PM PDT 24
Peak memory 257512 kb
Host smart-47321772-f28d-45b8-bc19-c4429cdb0ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038362853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1038362853
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1475235779
Short name T841
Test name
Test status
Simulation time 850607971 ps
CPU time 10.11 seconds
Started Jun 22 06:12:25 PM PDT 24
Finished Jun 22 06:12:35 PM PDT 24
Peak memory 224688 kb
Host smart-e5e991ff-1e67-4bd2-9032-e67f91080e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475235779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1475235779
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1985380740
Short name T219
Test name
Test status
Simulation time 1443863278 ps
CPU time 4.16 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:31 PM PDT 24
Peak memory 224644 kb
Host smart-053a0db9-cf3d-474b-b425-49ed9eb3b439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985380740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1985380740
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2310218481
Short name T276
Test name
Test status
Simulation time 1313546834 ps
CPU time 15.47 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:43 PM PDT 24
Peak memory 224716 kb
Host smart-844b25c8-57a9-473f-a390-e571fa7aba6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310218481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2310218481
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1771701454
Short name T750
Test name
Test status
Simulation time 2185403563 ps
CPU time 5.36 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:33 PM PDT 24
Peak memory 232968 kb
Host smart-0d8976d8-e1d4-4704-80d5-cbaef68c59c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771701454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1771701454
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3341387694
Short name T281
Test name
Test status
Simulation time 985224738 ps
CPU time 10.89 seconds
Started Jun 22 06:12:25 PM PDT 24
Finished Jun 22 06:12:37 PM PDT 24
Peak memory 240672 kb
Host smart-be84e700-2d4c-4b5c-9345-dbaf14d03212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341387694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3341387694
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2499887737
Short name T467
Test name
Test status
Simulation time 4033352501 ps
CPU time 9.87 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:38 PM PDT 24
Peak memory 223484 kb
Host smart-e070a05b-a267-49c6-99d2-1a6dade3b37a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2499887737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2499887737
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1461231640
Short name T554
Test name
Test status
Simulation time 1882546594 ps
CPU time 11.25 seconds
Started Jun 22 06:12:29 PM PDT 24
Finished Jun 22 06:12:41 PM PDT 24
Peak memory 235700 kb
Host smart-ed07112e-4221-4c04-a048-9bffafb7739e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461231640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1461231640
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2337303558
Short name T67
Test name
Test status
Simulation time 1055931497 ps
CPU time 5.91 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:33 PM PDT 24
Peak memory 216744 kb
Host smart-8e9e73da-5ce2-481c-a774-047d48ef4126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337303558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2337303558
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.390856015
Short name T483
Test name
Test status
Simulation time 1845762298 ps
CPU time 5.72 seconds
Started Jun 22 06:12:29 PM PDT 24
Finished Jun 22 06:12:36 PM PDT 24
Peak memory 216384 kb
Host smart-66b048d4-9a63-4bc1-b0a1-2990b29d9bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390856015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.390856015
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.891906613
Short name T942
Test name
Test status
Simulation time 74580087 ps
CPU time 1.24 seconds
Started Jun 22 06:12:25 PM PDT 24
Finished Jun 22 06:12:27 PM PDT 24
Peak memory 216452 kb
Host smart-ed49ffbd-693f-4b8c-ac7d-0665b51121b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891906613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.891906613
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.86908171
Short name T362
Test name
Test status
Simulation time 16986120 ps
CPU time 0.81 seconds
Started Jun 22 06:12:28 PM PDT 24
Finished Jun 22 06:12:31 PM PDT 24
Peak memory 206108 kb
Host smart-9ab92fa1-d39d-4387-9eff-909529644049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86908171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.86908171
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.144847972
Short name T595
Test name
Test status
Simulation time 3916487214 ps
CPU time 8.56 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:36 PM PDT 24
Peak memory 233024 kb
Host smart-6924d2e0-402d-4240-b392-2dd37584d151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144847972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.144847972
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2532339003
Short name T374
Test name
Test status
Simulation time 23678187 ps
CPU time 0.73 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:28 PM PDT 24
Peak memory 205528 kb
Host smart-137e8e2a-c468-4d16-ac69-902036103326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532339003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2532339003
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1504254589
Short name T262
Test name
Test status
Simulation time 1411081418 ps
CPU time 6.59 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:33 PM PDT 24
Peak memory 232864 kb
Host smart-2a40c130-2ee3-4963-975b-58d6d8029dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504254589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1504254589
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.448469798
Short name T760
Test name
Test status
Simulation time 14193947 ps
CPU time 0.82 seconds
Started Jun 22 06:12:28 PM PDT 24
Finished Jun 22 06:12:31 PM PDT 24
Peak memory 206692 kb
Host smart-c56861db-464f-46a7-9dc4-26caa85c4a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448469798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.448469798
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.238878543
Short name T550
Test name
Test status
Simulation time 26358434422 ps
CPU time 115.04 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:14:24 PM PDT 24
Peak memory 251772 kb
Host smart-92e8c7fe-ea18-4e3e-bc67-de32780e055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238878543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.238878543
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.457266747
Short name T818
Test name
Test status
Simulation time 7648542253 ps
CPU time 74.36 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:13:43 PM PDT 24
Peak memory 249320 kb
Host smart-abc60631-f97e-4815-8d91-44a9568f4ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457266747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.457266747
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3459797871
Short name T590
Test name
Test status
Simulation time 65060578767 ps
CPU time 277.7 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:17:07 PM PDT 24
Peak memory 265320 kb
Host smart-88c8173b-e7ec-467b-8e22-9362b0c68674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459797871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3459797871
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1547533017
Short name T716
Test name
Test status
Simulation time 20832808359 ps
CPU time 30.76 seconds
Started Jun 22 06:12:28 PM PDT 24
Finished Jun 22 06:13:01 PM PDT 24
Peak memory 232948 kb
Host smart-2a05a6f0-a0d6-4086-bfa2-eb57773a4314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547533017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1547533017
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.200129330
Short name T763
Test name
Test status
Simulation time 413732080 ps
CPU time 5.82 seconds
Started Jun 22 06:12:34 PM PDT 24
Finished Jun 22 06:12:41 PM PDT 24
Peak memory 232888 kb
Host smart-018c1a00-fdfa-436a-a739-9beb1bf4ca00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200129330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.200129330
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3185396119
Short name T944
Test name
Test status
Simulation time 270413618 ps
CPU time 8.12 seconds
Started Jun 22 06:12:25 PM PDT 24
Finished Jun 22 06:12:34 PM PDT 24
Peak memory 240988 kb
Host smart-0993df12-7d0e-4789-b957-ec9d6b01d419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185396119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3185396119
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.466690673
Short name T523
Test name
Test status
Simulation time 15681150350 ps
CPU time 12.46 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:41 PM PDT 24
Peak memory 224716 kb
Host smart-46d155d1-58ad-457c-86b1-e4ed0d05f103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466690673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.466690673
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.947750175
Short name T466
Test name
Test status
Simulation time 10526698820 ps
CPU time 28.66 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:12:57 PM PDT 24
Peak memory 240732 kb
Host smart-cfb5bdba-68ed-4dbd-b725-1f6b64409423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947750175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.947750175
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.351115049
Short name T655
Test name
Test status
Simulation time 112896494 ps
CPU time 4.21 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:31 PM PDT 24
Peak memory 223176 kb
Host smart-96ff9a83-520d-44c0-99a9-45b3d9f41f74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=351115049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.351115049
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4268072963
Short name T29
Test name
Test status
Simulation time 5141775678 ps
CPU time 24.64 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:53 PM PDT 24
Peak memory 216572 kb
Host smart-1fd1e007-6ba7-4c6d-ba2e-05fa41cfe361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268072963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4268072963
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1421224103
Short name T911
Test name
Test status
Simulation time 683817152 ps
CPU time 4.31 seconds
Started Jun 22 06:12:26 PM PDT 24
Finished Jun 22 06:12:32 PM PDT 24
Peak memory 216416 kb
Host smart-2dea5c0b-6a39-4ee3-ac29-9ed5c58dc817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421224103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1421224103
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3648191246
Short name T331
Test name
Test status
Simulation time 484231985 ps
CPU time 1 seconds
Started Jun 22 06:12:28 PM PDT 24
Finished Jun 22 06:12:31 PM PDT 24
Peak memory 206780 kb
Host smart-5ace5e2d-99c1-4cee-a1cd-9a33c3982ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648191246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3648191246
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.625048575
Short name T352
Test name
Test status
Simulation time 122638343 ps
CPU time 0.86 seconds
Started Jun 22 06:12:29 PM PDT 24
Finished Jun 22 06:12:31 PM PDT 24
Peak memory 206216 kb
Host smart-bed4b0df-25e7-4081-aacb-afd6eea4f7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625048575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.625048575
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1549908493
Short name T690
Test name
Test status
Simulation time 1411371572 ps
CPU time 8.91 seconds
Started Jun 22 06:12:27 PM PDT 24
Finished Jun 22 06:12:38 PM PDT 24
Peak memory 232888 kb
Host smart-77f825bd-c2a3-42ce-bc04-4bb1ee86a853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549908493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1549908493
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.4189147176
Short name T366
Test name
Test status
Simulation time 42577889 ps
CPU time 0.74 seconds
Started Jun 22 06:09:41 PM PDT 24
Finished Jun 22 06:09:43 PM PDT 24
Peak memory 205508 kb
Host smart-551adc20-685c-40fe-9bb3-bdf2b6be1f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189147176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4
189147176
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1909550891
Short name T723
Test name
Test status
Simulation time 30427385 ps
CPU time 2.17 seconds
Started Jun 22 06:09:40 PM PDT 24
Finished Jun 22 06:09:43 PM PDT 24
Peak memory 224616 kb
Host smart-a6abdc67-68e1-404c-9f58-b975815553a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909550891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1909550891
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2351570811
Short name T904
Test name
Test status
Simulation time 94642656 ps
CPU time 0.79 seconds
Started Jun 22 06:09:43 PM PDT 24
Finished Jun 22 06:09:45 PM PDT 24
Peak memory 206748 kb
Host smart-bc4239fd-59b8-44c3-8568-256989d4996d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351570811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2351570811
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.255320744
Short name T780
Test name
Test status
Simulation time 3193257799 ps
CPU time 55.06 seconds
Started Jun 22 06:09:44 PM PDT 24
Finished Jun 22 06:10:40 PM PDT 24
Peak memory 250192 kb
Host smart-0377c6d1-f790-459a-bf50-39b401c26487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255320744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.255320744
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3846611701
Short name T745
Test name
Test status
Simulation time 3044623707 ps
CPU time 54.89 seconds
Started Jun 22 06:09:41 PM PDT 24
Finished Jun 22 06:10:37 PM PDT 24
Peak memory 241240 kb
Host smart-f236a061-f996-4158-8d46-a34627164ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846611701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3846611701
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3300299968
Short name T949
Test name
Test status
Simulation time 32379191951 ps
CPU time 123.05 seconds
Started Jun 22 06:09:42 PM PDT 24
Finished Jun 22 06:11:46 PM PDT 24
Peak memory 256372 kb
Host smart-67b553be-b030-4878-96a2-6b59ce52f83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300299968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3300299968
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.589412440
Short name T238
Test name
Test status
Simulation time 178891113 ps
CPU time 5.32 seconds
Started Jun 22 06:09:45 PM PDT 24
Finished Jun 22 06:09:51 PM PDT 24
Peak memory 249232 kb
Host smart-9cd22958-19c2-4ee8-ac87-ece646e30952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589412440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.589412440
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.761974923
Short name T909
Test name
Test status
Simulation time 3706996060 ps
CPU time 13.93 seconds
Started Jun 22 06:09:42 PM PDT 24
Finished Jun 22 06:09:57 PM PDT 24
Peak memory 232948 kb
Host smart-44411464-119d-4966-820d-36bd4fe348d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761974923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.761974923
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.812971553
Short name T515
Test name
Test status
Simulation time 7040208891 ps
CPU time 28.06 seconds
Started Jun 22 06:09:42 PM PDT 24
Finished Jun 22 06:10:10 PM PDT 24
Peak memory 224656 kb
Host smart-a011f9d1-03b3-418b-ac17-0aff934f3a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812971553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.812971553
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1997766344
Short name T601
Test name
Test status
Simulation time 424666754 ps
CPU time 8 seconds
Started Jun 22 06:09:41 PM PDT 24
Finished Jun 22 06:09:50 PM PDT 24
Peak memory 240956 kb
Host smart-fb60e16e-fbb7-42e3-8c3a-ccef467aa283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997766344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1997766344
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3629532066
Short name T369
Test name
Test status
Simulation time 704442521 ps
CPU time 5.15 seconds
Started Jun 22 06:09:43 PM PDT 24
Finished Jun 22 06:09:49 PM PDT 24
Peak memory 224636 kb
Host smart-557849a0-b1ea-4d4d-8e0e-5a5f178c53e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629532066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3629532066
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3566138160
Short name T790
Test name
Test status
Simulation time 1019284492 ps
CPU time 4.05 seconds
Started Jun 22 06:09:42 PM PDT 24
Finished Jun 22 06:09:46 PM PDT 24
Peak memory 222136 kb
Host smart-51565e95-2bdb-4618-aff0-06fa603519a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3566138160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3566138160
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1814607970
Short name T162
Test name
Test status
Simulation time 25525934476 ps
CPU time 254.98 seconds
Started Jun 22 06:09:44 PM PDT 24
Finished Jun 22 06:13:59 PM PDT 24
Peak memory 253496 kb
Host smart-42ad4b37-9993-495f-8144-99715ec41486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814607970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1814607970
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.92698879
Short name T389
Test name
Test status
Simulation time 75147568 ps
CPU time 0.76 seconds
Started Jun 22 06:09:41 PM PDT 24
Finished Jun 22 06:09:43 PM PDT 24
Peak memory 205796 kb
Host smart-9a6e7216-d449-47ce-9d7f-c58484fb5804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92698879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.92698879
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.4145716358
Short name T803
Test name
Test status
Simulation time 35946902 ps
CPU time 0.71 seconds
Started Jun 22 06:09:44 PM PDT 24
Finished Jun 22 06:09:46 PM PDT 24
Peak memory 205756 kb
Host smart-94069c6c-f26f-42a6-bdac-49543318d98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145716358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.4145716358
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.879720019
Short name T617
Test name
Test status
Simulation time 599027905 ps
CPU time 2.6 seconds
Started Jun 22 06:09:40 PM PDT 24
Finished Jun 22 06:09:43 PM PDT 24
Peak memory 216456 kb
Host smart-fda1736a-4133-4aac-b0d3-94f4a6938089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879720019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.879720019
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1992622410
Short name T625
Test name
Test status
Simulation time 37749689 ps
CPU time 0.81 seconds
Started Jun 22 06:09:44 PM PDT 24
Finished Jun 22 06:09:45 PM PDT 24
Peak memory 206096 kb
Host smart-74b1bf93-8fb8-4c3f-9003-ebbea61d427b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992622410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1992622410
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3866741599
Short name T583
Test name
Test status
Simulation time 621847405 ps
CPU time 3.93 seconds
Started Jun 22 06:09:42 PM PDT 24
Finished Jun 22 06:09:47 PM PDT 24
Peak memory 224664 kb
Host smart-bebbd990-16d3-46e0-9b59-71b3f0b1fff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866741599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3866741599
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.739445573
Short name T592
Test name
Test status
Simulation time 15013315 ps
CPU time 0.72 seconds
Started Jun 22 06:09:49 PM PDT 24
Finished Jun 22 06:09:51 PM PDT 24
Peak memory 205856 kb
Host smart-695e6bda-4ec6-4991-8d82-083397f6776e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739445573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.739445573
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1209466617
Short name T174
Test name
Test status
Simulation time 1347962766 ps
CPU time 5.56 seconds
Started Jun 22 06:09:44 PM PDT 24
Finished Jun 22 06:09:50 PM PDT 24
Peak memory 232880 kb
Host smart-672b7f03-ac02-42c1-96b2-2f91844a8702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209466617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1209466617
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1464352936
Short name T695
Test name
Test status
Simulation time 32555615 ps
CPU time 0.81 seconds
Started Jun 22 06:09:44 PM PDT 24
Finished Jun 22 06:09:45 PM PDT 24
Peak memory 205848 kb
Host smart-f84580c4-1391-4c52-a590-dcb7c3caab8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464352936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1464352936
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1588337619
Short name T654
Test name
Test status
Simulation time 862216011 ps
CPU time 8.19 seconds
Started Jun 22 06:09:53 PM PDT 24
Finished Jun 22 06:10:02 PM PDT 24
Peak memory 241060 kb
Host smart-224a4a03-4159-439d-9ee6-3dd9ac1186dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588337619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1588337619
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2890949388
Short name T646
Test name
Test status
Simulation time 145488166271 ps
CPU time 363.21 seconds
Started Jun 22 06:09:47 PM PDT 24
Finished Jun 22 06:15:51 PM PDT 24
Peak memory 257600 kb
Host smart-7c094972-fbc1-4fb9-af95-8a2997e6f5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890949388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2890949388
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.200392349
Short name T297
Test name
Test status
Simulation time 299000742180 ps
CPU time 572.31 seconds
Started Jun 22 06:09:58 PM PDT 24
Finished Jun 22 06:19:31 PM PDT 24
Peak memory 258664 kb
Host smart-ef62f775-9a73-473a-b568-91704229c40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200392349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
200392349
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4058522158
Short name T313
Test name
Test status
Simulation time 20524344653 ps
CPU time 70.7 seconds
Started Jun 22 06:09:48 PM PDT 24
Finished Jun 22 06:10:59 PM PDT 24
Peak memory 237352 kb
Host smart-27b461f7-ccd8-45bc-9a07-5fd9a25f4d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058522158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4058522158
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3372161108
Short name T836
Test name
Test status
Simulation time 545443073 ps
CPU time 6.44 seconds
Started Jun 22 06:09:42 PM PDT 24
Finished Jun 22 06:09:50 PM PDT 24
Peak memory 232876 kb
Host smart-ea33042a-b406-49f2-9b99-0ba94bcaec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372161108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3372161108
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.615089477
Short name T106
Test name
Test status
Simulation time 1075022482 ps
CPU time 6.47 seconds
Started Jun 22 06:09:48 PM PDT 24
Finished Jun 22 06:09:55 PM PDT 24
Peak memory 232892 kb
Host smart-4a4cd2c8-a7b8-4c64-9a03-f8cb9637d78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615089477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.615089477
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2410340312
Short name T959
Test name
Test status
Simulation time 251146131 ps
CPU time 3.95 seconds
Started Jun 22 06:09:40 PM PDT 24
Finished Jun 22 06:09:45 PM PDT 24
Peak memory 224616 kb
Host smart-e41b2552-851d-40b7-ba6f-94f088959293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410340312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2410340312
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1655900948
Short name T387
Test name
Test status
Simulation time 16382387873 ps
CPU time 12.65 seconds
Started Jun 22 06:09:43 PM PDT 24
Finished Jun 22 06:09:57 PM PDT 24
Peak memory 233088 kb
Host smart-e767185e-085c-4221-9956-75cc5eadc02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655900948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1655900948
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1587564204
Short name T399
Test name
Test status
Simulation time 106503596 ps
CPU time 4.03 seconds
Started Jun 22 06:09:48 PM PDT 24
Finished Jun 22 06:09:53 PM PDT 24
Peak memory 223176 kb
Host smart-764e615d-a7b1-43e6-8848-ace1ae7d28c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1587564204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1587564204
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1169677077
Short name T333
Test name
Test status
Simulation time 4418484714 ps
CPU time 27.74 seconds
Started Jun 22 06:09:42 PM PDT 24
Finished Jun 22 06:10:11 PM PDT 24
Peak memory 216576 kb
Host smart-ece4e548-2fba-4f02-8ec9-0e418b40c6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169677077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1169677077
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2782930640
Short name T754
Test name
Test status
Simulation time 12469390423 ps
CPU time 17.29 seconds
Started Jun 22 06:09:41 PM PDT 24
Finished Jun 22 06:09:59 PM PDT 24
Peak memory 216516 kb
Host smart-ff6f6614-7603-423b-8004-becc3416dc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782930640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2782930640
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1581951178
Short name T752
Test name
Test status
Simulation time 22751186 ps
CPU time 1.05 seconds
Started Jun 22 06:09:42 PM PDT 24
Finished Jun 22 06:09:44 PM PDT 24
Peak memory 207596 kb
Host smart-fe609eb7-7ed8-4ae0-bf65-59a4def05d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581951178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1581951178
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3030424731
Short name T34
Test name
Test status
Simulation time 160753706 ps
CPU time 0.81 seconds
Started Jun 22 06:09:47 PM PDT 24
Finished Jun 22 06:09:49 PM PDT 24
Peak memory 206100 kb
Host smart-a4d7fa5b-a453-4aaf-9b11-5e5682575f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030424731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3030424731
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1288493830
Short name T368
Test name
Test status
Simulation time 88740252 ps
CPU time 2.24 seconds
Started Jun 22 06:09:51 PM PDT 24
Finished Jun 22 06:09:53 PM PDT 24
Peak memory 223532 kb
Host smart-a822f701-d469-4891-aa31-dee7b4175b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288493830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1288493830
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4031610522
Short name T339
Test name
Test status
Simulation time 56846340 ps
CPU time 0.72 seconds
Started Jun 22 06:09:48 PM PDT 24
Finished Jun 22 06:09:49 PM PDT 24
Peak memory 205536 kb
Host smart-25f3c602-69a9-4f8f-810d-6506f54fa3a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031610522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
031610522
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2994754241
Short name T587
Test name
Test status
Simulation time 610391232 ps
CPU time 5.55 seconds
Started Jun 22 06:09:58 PM PDT 24
Finished Jun 22 06:10:04 PM PDT 24
Peak memory 232824 kb
Host smart-fc22b4cc-fe64-467e-833a-066307ca77e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994754241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2994754241
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2428778953
Short name T144
Test name
Test status
Simulation time 17077643 ps
CPU time 0.8 seconds
Started Jun 22 06:09:47 PM PDT 24
Finished Jun 22 06:09:48 PM PDT 24
Peak memory 207060 kb
Host smart-4e3144d8-c735-43b5-ad7c-53f2f84eaee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428778953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2428778953
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3490419953
Short name T517
Test name
Test status
Simulation time 12483135950 ps
CPU time 80.02 seconds
Started Jun 22 06:09:51 PM PDT 24
Finished Jun 22 06:11:11 PM PDT 24
Peak memory 241396 kb
Host smart-2e1b65c5-b0fa-4a1e-a82e-06c48434a89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490419953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3490419953
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.4193193019
Short name T87
Test name
Test status
Simulation time 11954932447 ps
CPU time 158.27 seconds
Started Jun 22 06:09:50 PM PDT 24
Finished Jun 22 06:12:29 PM PDT 24
Peak memory 250468 kb
Host smart-a732435e-b66d-45cb-9ce0-763205ad24e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193193019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4193193019
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.4066827033
Short name T217
Test name
Test status
Simulation time 150671736804 ps
CPU time 393.91 seconds
Started Jun 22 06:09:50 PM PDT 24
Finished Jun 22 06:16:25 PM PDT 24
Peak memory 273676 kb
Host smart-76cc1afc-7711-4ee1-ae5b-1aaa3ad99cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066827033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.4066827033
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3671883639
Short name T534
Test name
Test status
Simulation time 93572246 ps
CPU time 3.11 seconds
Started Jun 22 06:09:47 PM PDT 24
Finished Jun 22 06:09:51 PM PDT 24
Peak memory 232892 kb
Host smart-c74ea9db-192a-4ff8-a30f-0624cc89d605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671883639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3671883639
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3913308094
Short name T633
Test name
Test status
Simulation time 617724229 ps
CPU time 8.68 seconds
Started Jun 22 06:09:52 PM PDT 24
Finished Jun 22 06:10:01 PM PDT 24
Peak memory 224644 kb
Host smart-27670a4d-7c3d-4818-8510-29c4a2831f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913308094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3913308094
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3446276937
Short name T464
Test name
Test status
Simulation time 561944567 ps
CPU time 7.95 seconds
Started Jun 22 06:09:51 PM PDT 24
Finished Jun 22 06:09:59 PM PDT 24
Peak memory 224588 kb
Host smart-4c406870-3616-4234-a748-3b140ab205c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446276937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3446276937
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3649055338
Short name T753
Test name
Test status
Simulation time 5146447065 ps
CPU time 7.28 seconds
Started Jun 22 06:09:54 PM PDT 24
Finished Jun 22 06:10:02 PM PDT 24
Peak memory 224744 kb
Host smart-774886f6-5393-4394-b81d-fa25c2744ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649055338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3649055338
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.361593817
Short name T565
Test name
Test status
Simulation time 6186644129 ps
CPU time 9.32 seconds
Started Jun 22 06:09:49 PM PDT 24
Finished Jun 22 06:09:59 PM PDT 24
Peak memory 232924 kb
Host smart-da0513b3-f567-48c3-8ebc-a722aa6b2ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361593817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.361593817
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4186608452
Short name T475
Test name
Test status
Simulation time 1250620140 ps
CPU time 6.16 seconds
Started Jun 22 06:09:51 PM PDT 24
Finished Jun 22 06:09:58 PM PDT 24
Peak memory 223336 kb
Host smart-3fd02c08-13e7-47d4-b2a3-75f52694bf8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4186608452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4186608452
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2962487214
Short name T380
Test name
Test status
Simulation time 109551845 ps
CPU time 1.23 seconds
Started Jun 22 06:09:52 PM PDT 24
Finished Jun 22 06:09:53 PM PDT 24
Peak memory 207224 kb
Host smart-73488ecb-b53f-4b42-bc61-31a977b27bbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962487214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2962487214
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3746358549
Short name T485
Test name
Test status
Simulation time 4051067796 ps
CPU time 5.4 seconds
Started Jun 22 06:09:50 PM PDT 24
Finished Jun 22 06:09:56 PM PDT 24
Peak memory 218404 kb
Host smart-98d52601-c5ee-4905-94e5-70d7803b1612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746358549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3746358549
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1698343678
Short name T799
Test name
Test status
Simulation time 7943414919 ps
CPU time 4.99 seconds
Started Jun 22 06:09:58 PM PDT 24
Finished Jun 22 06:10:04 PM PDT 24
Peak memory 216432 kb
Host smart-82e0374b-fa22-494d-a52d-12452f56baad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698343678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1698343678
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4089740273
Short name T692
Test name
Test status
Simulation time 139094517 ps
CPU time 0.79 seconds
Started Jun 22 06:09:49 PM PDT 24
Finished Jun 22 06:09:51 PM PDT 24
Peak memory 206068 kb
Host smart-5b729631-bc31-434d-9d83-6feeb93ea660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089740273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4089740273
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.959240141
Short name T714
Test name
Test status
Simulation time 23318156 ps
CPU time 0.73 seconds
Started Jun 22 06:09:49 PM PDT 24
Finished Jun 22 06:09:50 PM PDT 24
Peak memory 206084 kb
Host smart-24331ffd-39be-4a8d-a25c-8baee3aa2a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959240141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.959240141
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1339640850
Short name T283
Test name
Test status
Simulation time 9806780353 ps
CPU time 19.9 seconds
Started Jun 22 06:09:47 PM PDT 24
Finished Jun 22 06:10:08 PM PDT 24
Peak memory 232896 kb
Host smart-c3ac8a1d-9726-42a2-8823-0e0cde451c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339640850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1339640850
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3990457720
Short name T885
Test name
Test status
Simulation time 13912914 ps
CPU time 0.77 seconds
Started Jun 22 06:09:57 PM PDT 24
Finished Jun 22 06:09:59 PM PDT 24
Peak memory 205516 kb
Host smart-6dda8a06-f814-4456-b122-98347906d900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990457720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
990457720
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.548170164
Short name T897
Test name
Test status
Simulation time 137381637 ps
CPU time 2.56 seconds
Started Jun 22 06:09:54 PM PDT 24
Finished Jun 22 06:09:58 PM PDT 24
Peak memory 224600 kb
Host smart-3f75a600-6e2a-4584-a3b7-dabed521abfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548170164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.548170164
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2062817816
Short name T503
Test name
Test status
Simulation time 62485535 ps
CPU time 0.8 seconds
Started Jun 22 06:09:52 PM PDT 24
Finished Jun 22 06:09:53 PM PDT 24
Peak memory 207280 kb
Host smart-10263c4f-345a-46ef-bb2d-7e50cfabb718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062817816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2062817816
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.70731362
Short name T781
Test name
Test status
Simulation time 32831954516 ps
CPU time 76.56 seconds
Started Jun 22 06:10:01 PM PDT 24
Finished Jun 22 06:11:18 PM PDT 24
Peak memory 236704 kb
Host smart-5e9b29e1-1319-4462-9482-0bc59cffa0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70731362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.70731362
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.639080560
Short name T199
Test name
Test status
Simulation time 31642074095 ps
CPU time 368.44 seconds
Started Jun 22 06:09:59 PM PDT 24
Finished Jun 22 06:16:08 PM PDT 24
Peak memory 263868 kb
Host smart-5366e02a-780e-4596-b4bc-11d1ea2a0455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639080560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.639080560
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3635014843
Short name T435
Test name
Test status
Simulation time 90121742229 ps
CPU time 199.03 seconds
Started Jun 22 06:09:55 PM PDT 24
Finished Jun 22 06:13:15 PM PDT 24
Peak memory 257624 kb
Host smart-5d250938-0ef2-409c-98a1-cb9a24d2580f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635014843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3635014843
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.310851951
Short name T310
Test name
Test status
Simulation time 11818726240 ps
CPU time 51.06 seconds
Started Jun 22 06:09:55 PM PDT 24
Finished Jun 22 06:10:46 PM PDT 24
Peak memory 224744 kb
Host smart-d56a566c-e6b4-4be6-971e-dd4e240ce9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310851951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.310851951
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2114019957
Short name T829
Test name
Test status
Simulation time 2054030276 ps
CPU time 13.69 seconds
Started Jun 22 06:09:47 PM PDT 24
Finished Jun 22 06:10:01 PM PDT 24
Peak memory 232852 kb
Host smart-07a2145b-8de1-48ab-93f8-9cb410132c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114019957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2114019957
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.185094823
Short name T557
Test name
Test status
Simulation time 108892737 ps
CPU time 2.4 seconds
Started Jun 22 06:09:56 PM PDT 24
Finished Jun 22 06:09:59 PM PDT 24
Peak memory 223280 kb
Host smart-330b5507-5965-4f83-b497-8c8ce7c3c6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185094823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.185094823
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3721762951
Short name T265
Test name
Test status
Simulation time 5069634878 ps
CPU time 6.78 seconds
Started Jun 22 06:09:53 PM PDT 24
Finished Jun 22 06:10:00 PM PDT 24
Peak memory 232972 kb
Host smart-66ea9723-013e-42fe-aafb-107b9ca59167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721762951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3721762951
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1513879694
Short name T259
Test name
Test status
Simulation time 4717832411 ps
CPU time 4.54 seconds
Started Jun 22 06:09:50 PM PDT 24
Finished Jun 22 06:09:55 PM PDT 24
Peak memory 224744 kb
Host smart-766cdfa8-8cd9-4cae-9b68-32bcdefecbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513879694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1513879694
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2200427823
Short name T650
Test name
Test status
Simulation time 106695811 ps
CPU time 4.22 seconds
Started Jun 22 06:09:55 PM PDT 24
Finished Jun 22 06:10:00 PM PDT 24
Peak memory 223192 kb
Host smart-5305a49f-0364-4347-a196-eb726882ee66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2200427823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2200427823
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3467838611
Short name T887
Test name
Test status
Simulation time 13298812049 ps
CPU time 121.09 seconds
Started Jun 22 06:09:58 PM PDT 24
Finished Jun 22 06:12:00 PM PDT 24
Peak memory 249424 kb
Host smart-47602bb2-735a-489f-be4f-069a72c536e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467838611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3467838611
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1685428514
Short name T361
Test name
Test status
Simulation time 1123491146 ps
CPU time 8.8 seconds
Started Jun 22 06:10:00 PM PDT 24
Finished Jun 22 06:10:09 PM PDT 24
Peak memory 216452 kb
Host smart-e107e826-21b6-446d-9682-815da960277b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685428514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1685428514
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.536602423
Short name T335
Test name
Test status
Simulation time 4435793664 ps
CPU time 13.78 seconds
Started Jun 22 06:09:58 PM PDT 24
Finished Jun 22 06:10:12 PM PDT 24
Peak memory 216492 kb
Host smart-e7558558-d391-42c0-bed4-c18cf651e2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536602423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.536602423
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2179400429
Short name T431
Test name
Test status
Simulation time 24568732 ps
CPU time 0.95 seconds
Started Jun 22 06:09:54 PM PDT 24
Finished Jun 22 06:09:55 PM PDT 24
Peak memory 207400 kb
Host smart-82fcc5c8-05b3-4641-b215-f6ed471d4b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179400429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2179400429
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1590402299
Short name T367
Test name
Test status
Simulation time 51998697 ps
CPU time 0.9 seconds
Started Jun 22 06:09:58 PM PDT 24
Finished Jun 22 06:10:00 PM PDT 24
Peak memory 207116 kb
Host smart-ffdd87ad-db7e-4d53-8e5e-6e99da999261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590402299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1590402299
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3067056067
Short name T270
Test name
Test status
Simulation time 27126968132 ps
CPU time 39.49 seconds
Started Jun 22 06:09:55 PM PDT 24
Finished Jun 22 06:10:36 PM PDT 24
Peak memory 249348 kb
Host smart-a58a85dd-ae96-401a-816f-f6a3b7f7fe8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067056067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3067056067
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4112378619
Short name T358
Test name
Test status
Simulation time 14202948 ps
CPU time 0.72 seconds
Started Jun 22 06:09:55 PM PDT 24
Finished Jun 22 06:09:57 PM PDT 24
Peak memory 204932 kb
Host smart-ec64554c-9585-4d0d-b5fb-e325c7915f48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112378619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
112378619
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.700334077
Short name T193
Test name
Test status
Simulation time 566266310 ps
CPU time 3.16 seconds
Started Jun 22 06:09:55 PM PDT 24
Finished Jun 22 06:09:59 PM PDT 24
Peak memory 224640 kb
Host smart-925971e3-caa5-4e57-8dba-a919fac97549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700334077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.700334077
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1646924256
Short name T536
Test name
Test status
Simulation time 14740691 ps
CPU time 0.81 seconds
Started Jun 22 06:09:56 PM PDT 24
Finished Jun 22 06:09:58 PM PDT 24
Peak memory 206704 kb
Host smart-266ef21b-4b43-45b4-95cb-11f812cba968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646924256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1646924256
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2458785710
Short name T778
Test name
Test status
Simulation time 46847474615 ps
CPU time 120.07 seconds
Started Jun 22 06:09:57 PM PDT 24
Finished Jun 22 06:11:58 PM PDT 24
Peak memory 256512 kb
Host smart-ad0f81fa-612f-44c5-9ff2-8e80ae850b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458785710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2458785710
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4164550068
Short name T36
Test name
Test status
Simulation time 40768970056 ps
CPU time 171.3 seconds
Started Jun 22 06:09:55 PM PDT 24
Finished Jun 22 06:12:47 PM PDT 24
Peak memory 249436 kb
Host smart-cb480b9a-54a1-437b-85fe-c376bd70dae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164550068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4164550068
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3134260025
Short name T325
Test name
Test status
Simulation time 2725657692 ps
CPU time 42.21 seconds
Started Jun 22 06:09:58 PM PDT 24
Finished Jun 22 06:10:41 PM PDT 24
Peak memory 249596 kb
Host smart-38560def-87da-4e7f-927a-41c2afc1c9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134260025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3134260025
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1919494718
Short name T737
Test name
Test status
Simulation time 2585409627 ps
CPU time 10.99 seconds
Started Jun 22 06:09:58 PM PDT 24
Finished Jun 22 06:10:10 PM PDT 24
Peak memory 241152 kb
Host smart-97d9e20a-5011-4860-ae8a-7cf87342b3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919494718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1919494718
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.4192944357
Short name T794
Test name
Test status
Simulation time 108003051 ps
CPU time 2.44 seconds
Started Jun 22 06:09:54 PM PDT 24
Finished Jun 22 06:09:57 PM PDT 24
Peak memory 232488 kb
Host smart-8ce8a4cf-6710-4405-a306-24c20fad66e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192944357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.4192944357
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2608834934
Short name T224
Test name
Test status
Simulation time 782698035 ps
CPU time 12.09 seconds
Started Jun 22 06:09:57 PM PDT 24
Finished Jun 22 06:10:10 PM PDT 24
Peak memory 239024 kb
Host smart-3c269939-f986-4129-ade2-26fdc0dae5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608834934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2608834934
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2427044237
Short name T282
Test name
Test status
Simulation time 4446195822 ps
CPU time 18.94 seconds
Started Jun 22 06:09:55 PM PDT 24
Finished Jun 22 06:10:15 PM PDT 24
Peak memory 236468 kb
Host smart-d7f37c89-23af-4bb0-a320-28b772feb1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427044237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2427044237
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3095801528
Short name T863
Test name
Test status
Simulation time 2954926849 ps
CPU time 13.76 seconds
Started Jun 22 06:09:53 PM PDT 24
Finished Jun 22 06:10:08 PM PDT 24
Peak memory 232980 kb
Host smart-38a92439-47ed-4644-932d-4450db935586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095801528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3095801528
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1980043371
Short name T546
Test name
Test status
Simulation time 1491865347 ps
CPU time 10.34 seconds
Started Jun 22 06:09:54 PM PDT 24
Finished Jun 22 06:10:06 PM PDT 24
Peak memory 223204 kb
Host smart-09944734-8ce1-402c-b1ef-2384255e7da9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1980043371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1980043371
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.298007790
Short name T294
Test name
Test status
Simulation time 183347165059 ps
CPU time 435.52 seconds
Started Jun 22 06:09:56 PM PDT 24
Finished Jun 22 06:17:12 PM PDT 24
Peak memory 265668 kb
Host smart-a846edd9-cca3-489d-b816-ad013413e6c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298007790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.298007790
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2976577991
Short name T808
Test name
Test status
Simulation time 1725308128 ps
CPU time 11.87 seconds
Started Jun 22 06:09:57 PM PDT 24
Finished Jun 22 06:10:10 PM PDT 24
Peak memory 220032 kb
Host smart-5ed58d28-f1c9-4d17-901b-7d8f7ad632b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976577991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2976577991
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.80000283
Short name T931
Test name
Test status
Simulation time 6600908362 ps
CPU time 16.48 seconds
Started Jun 22 06:10:08 PM PDT 24
Finished Jun 22 06:10:25 PM PDT 24
Peak memory 216496 kb
Host smart-52e4bdb5-dc6b-4aaa-a256-fa9a925bb985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80000283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.80000283
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2479569995
Short name T137
Test name
Test status
Simulation time 110857621 ps
CPU time 1.32 seconds
Started Jun 22 06:09:54 PM PDT 24
Finished Jun 22 06:09:56 PM PDT 24
Peak memory 216448 kb
Host smart-2267ceae-bde5-446d-89a6-ef77259c9a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479569995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2479569995
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3235838755
Short name T658
Test name
Test status
Simulation time 120925222 ps
CPU time 0.76 seconds
Started Jun 22 06:09:55 PM PDT 24
Finished Jun 22 06:09:57 PM PDT 24
Peak memory 206068 kb
Host smart-1591b3d1-48d0-40f1-8ba9-3b49549c744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235838755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3235838755
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4062655416
Short name T957
Test name
Test status
Simulation time 139958643 ps
CPU time 2.57 seconds
Started Jun 22 06:09:57 PM PDT 24
Finished Jun 22 06:10:00 PM PDT 24
Peak memory 224700 kb
Host smart-062c684b-2824-4bc0-b14d-938a70843425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062655416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4062655416
Directory /workspace/9.spi_device_upload/latest
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