Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2657286	1			T1	1		T2	2842		T3	14206
all_values[1]	2657286	1			T1	1		T2	2842		T3	14206
all_values[2]	2657286	1			T1	1		T2	2842		T3	14206
all_values[3]	2657286	1			T1	1		T2	2842		T3	14206
all_values[4]	2657286	1			T1	1		T2	2842		T3	14206
all_values[5]	2657286	1			T1	1		T2	2842		T3	14206
all_values[6]	2657286	1			T1	1		T2	2842		T3	14206
all_values[7]	2657286	1			T1	1		T2	2842		T3	14206

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20120297

1

T1

8

T2

22736

T3

113633

auto[1]

1137991

1

T3

15

T14

108046

T15

333094

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21229502

1

T1

8

T2

22736

T3

113537

auto[1]

28786

1

T3

111

T28

9

T29

120

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2440990	1			T1	1		T2	2842		T3	14127
all_values[0]	auto[0]	auto[1]	12900	1			T3	79		T28	3		T29	87
all_values[0]	auto[1]	auto[0]	202685	1			T15	87006		T16	4138		T19	2
all_values[0]	auto[1]	auto[1]	711	1			T14	2		T15	155		T16	50
all_values[1]	auto[0]	auto[0]	2467288	1			T1	1		T2	2842		T3	14193
all_values[1]	auto[0]	auto[1]	8551	1			T3	8		T28	3		T29	20
all_values[1]	auto[1]	auto[0]	180583	1			T3	1		T14	26748		T15	35669
all_values[1]	auto[1]	auto[1]	864	1			T3	4		T14	259		T15	132
all_values[2]	auto[0]	auto[0]	2440504	1			T1	1		T2	2842		T3	14196
all_values[2]	auto[0]	auto[1]	3702	1			T3	8		T28	3		T29	13
all_values[2]	auto[1]	auto[0]	212719	1			T3	1		T14	4		T15	122835
all_values[2]	auto[1]	auto[1]	361	1			T3	1		T15	118		T16	16
all_values[3]	auto[0]	auto[0]	2597965	1			T1	1		T2	2842		T3	14202
all_values[3]	auto[0]	auto[1]	174	1			T3	4		T14	4		T15	1
all_values[3]	auto[1]	auto[0]	58966	1			T14	1		T15	3		T16	4193
all_values[3]	auto[1]	auto[1]	181	1			T14	5		T19	2		T21	3
all_values[4]	auto[0]	auto[0]	2424572	1			T1	1		T2	2842		T3	14204
all_values[4]	auto[0]	auto[1]	159	1			T3	2		T14	2		T15	5
all_values[4]	auto[1]	auto[0]	232367	1			T14	27005		T15	87157		T16	4187
all_values[4]	auto[1]	auto[1]	188	1			T15	5		T16	6		T19	1
all_values[5]	auto[0]	auto[0]	2564718	1			T1	1		T2	2842		T3	14204
all_values[5]	auto[0]	auto[1]	169	1			T3	1		T14	1		T15	7
all_values[5]	auto[1]	auto[0]	92257	1			T14	27006		T15	1		T16	4187
all_values[5]	auto[1]	auto[1]	142	1			T3	1		T14	3		T15	3
all_values[6]	auto[0]	auto[0]	2591427	1			T1	1		T2	2842		T3	14204
all_values[6]	auto[0]	auto[1]	191	1			T14	1		T15	4		T16	2
all_values[6]	auto[1]	auto[0]	65505	1			T3	2		T14	3		T15	4
all_values[6]	auto[1]	auto[1]	163	1			T14	3		T15	1		T21	3
all_values[7]	auto[0]	auto[0]	2566807	1			T1	1		T2	2842		T3	14201
all_values[7]	auto[0]	auto[1]	180	1			T14	1		T15	4		T19	5
all_values[7]	auto[1]	auto[0]	90149	1			T3	2		T14	27004		T15	5
all_values[7]	auto[1]	auto[1]	150	1			T3	3		T14	3		T16	3