Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35565	1			T1	6		T2	220		T3	59
auto[SpiFlashAddrCfg]	6699	1			T1	2		T2	35		T3	18
auto[SpiFlashAddr3b]	8016	1			T2	23		T3	30		T6	2
auto[SpiFlashAddr4b]	6753	1			T1	12		T2	32		T3	26

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31467

1

T2

80

T3

78

T6

16

auto[1]

25566

1

T1

20

T2

230

T3

55

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29995

1

T1

14

T2

153

T3

70

auto[1]

27038

1

T1

6

T2

157

T3

63

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39787	1			T1	6		T2	234		T3	76
values[1]	1008	1			T2	5		T3	3		T7	3
values[2]	1309	1			T2	5		T3	8		T7	3
values[3]	1250	1			T2	8		T3	4		T7	4
values[4]	1182	1			T1	10		T2	2		T3	5
values[5]	1280	1			T2	6		T3	2		T6	2
values[6]	1259	1			T2	2		T3	2		T7	4
values[7]	1364	1			T2	10		T3	8		T7	12
values[8]	8594	1			T1	4		T2	38		T3	25

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26373

1

T1

20

T2

310

T6

16

auto[1]

30660

1

T3

133

T11

5

T34

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54124

1

T1

14

T2

290

T3

127

write

2909

1

T1

6

T2

20

T3

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16783

1

T1

12

T2

65

T3

57

valids[0x1]

40250

1

T1

8

T2

245

T3

76

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1405	1			T2	6		T3	4		T7	6
internal_process_ops[0x5a]	1400	1			T2	2		T3	3		T7	5
internal_process_ops[0x05]	23302	1			T2	177		T3	15		T6	4
internal_process_ops[0x35]	1361	1			T2	4		T3	9		T7	3
internal_process_ops[0x15]	1377	1			T2	4		T3	5		T6	2
internal_process_ops[0x03]	905	1			T2	4		T7	5		T33	3
internal_process_ops[0x0b]	967	1			T2	3		T3	4		T7	5
internal_process_ops[0x3b]	852	1			T2	5		T3	2		T7	6
internal_process_ops[0x6b]	976	1			T2	1		T3	4		T7	6
internal_process_ops[0xbb]	868	1			T2	4		T7	2		T11	3
internal_process_ops[0xeb]	922	1			T2	11		T3	2		T7	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55661

1

T1

14

T2

299

T3

132

auto[1]

1372

1

T1

6

T2

11

T3

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54938

1

T1

20

T2

298

T3

124

auto[1]

2095

1

T2

12

T3

9

T7

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8841

1

T2

35

T6

10

T7

90

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6087

1

T2

182

T7

66

T37

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1737

1

T2

11

T7

5

T8

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1496

1

T1

2

T2

14

T7

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2002

1

T2

8

T7

14

T8

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1761

1

T2

10

T7

17

T37

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1594

1

T2

19

T6

2

T7

11

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1594

1

T1

12

T2

11

T7

17

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

87

1

T2

1

T6

2

T7

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

85

1

T2

1

T7

3

T15

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

75

1

T2

1

T29

1

T31

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

79

1

T1

6

T29

2

T31

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

84

1

T2

2

T9

2

T31

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

51

1

T29

1

T31

1

T41

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

79

1

T2

2

T7

2

T29

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

94

1

T2

6

T31

1

T15

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

113

1

T2

2

T6

2

T7

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

62

1

T15

3

T166

2

T167

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

69

1

T127

2

T132

2

T168

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

85

1

T2

3

T7

1

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

93

1

T7

2

T9

6

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

69

1

T2

1

T7

2

T29

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

63

1

T2

1

T30

2

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

73

1

T37

2

T39

4

T15

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11257

1

T3

37

T33

22

T28

173

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8626

1

T3

19

T33

24

T28

152

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1396

1

T3

9

T11

5

T34

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1329

1

T3

9

T33

1

T28

23

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1765

1

T3

17

T33

12

T28

27

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1770

1

T3

13

T33

11

T28

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1424

1

T3

12

T33

12

T89

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1445

1

T3

11

T33

12

T28

11

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

113

1

T3

3

T33

1

T43

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

91

1

T33

1

T14

2

T165

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

129

1

T33

2

T28

1

T43

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

95

1

T28

4

T43

2

T14

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

109

1

T14

4

T159

1

T165

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

101

1

T33

2

T28

3

T43

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

120

1

T33

3

T28

1

T43

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

103

1

T28

1

T43

1

T165

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

82

1

T28

2

T43

2

T44

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

108

1

T14

1

T15

5

T130

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

114

1

T28

2

T43

2

T14

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

85

1

T33

1

T43

2

T14

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

108

1

T33

1

T28

3

T43

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

95

1

T33

1

T28

1

T43

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

99

1

T3

2

T14

1

T159

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

96

1

T3

1

T43

4

T14

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3037	1			T2	16		T6	4		T7	19
auto[0]	values[0]	valids[0x1]	14238	1			T1	6		T2	218		T6	10
auto[0]	values[1]	valids[0x1]	506	1			T2	5		T7	3		T42	2
auto[0]	values[2]	valids[0x0]	469	1			T2	5		T7	3		T8	4
auto[0]	values[2]	valids[0x1]	245	1			T29	1		T31	3		T15	4
auto[0]	values[3]	valids[0x0]	438	1			T2	7		T7	4		T30	4
auto[0]	values[3]	valids[0x1]	239	1			T2	1		T29	2		T31	7
auto[0]	values[4]	valids[0x0]	423	1			T1	10		T2	1		T7	2
auto[0]	values[4]	valids[0x1]	179	1			T2	1		T7	1		T37	6
auto[0]	values[5]	valids[0x0]	425	1			T2	2		T6	2		T7	4
auto[0]	values[5]	valids[0x1]	221	1			T2	4		T7	5		T8	2
auto[0]	values[6]	valids[0x0]	424	1			T2	2		T7	4		T29	2
auto[0]	values[6]	valids[0x1]	254	1			T10	2		T29	3		T31	2
auto[0]	values[7]	valids[0x0]	452	1			T2	2		T7	2		T29	1
auto[0]	values[7]	valids[0x1]	274	1			T2	8		T7	10		T42	2
auto[0]	values[8]	valids[0x0]	2859	1			T1	2		T2	30		T7	21
auto[0]	values[8]	valids[0x1]	1690	1			T1	2		T2	8		T7	17
auto[1]	values[0]	valids[0x0]	3797	1			T3	30		T33	9		T28	44
auto[1]	values[0]	valids[0x1]	18715	1			T3	46		T33	50		T28	318
auto[1]	values[1]	valids[0x1]	502	1			T3	3		T33	7		T28	9
auto[1]	values[2]	valids[0x0]	355	1			T3	5		T33	2		T28	2
auto[1]	values[2]	valids[0x1]	240	1			T3	3		T33	1		T43	1
auto[1]	values[3]	valids[0x0]	332	1			T28	4		T43	12		T44	2
auto[1]	values[3]	valids[0x1]	241	1			T3	4		T28	2		T43	2
auto[1]	values[4]	valids[0x0]	352	1			T3	1		T33	3		T28	5
auto[1]	values[4]	valids[0x1]	228	1			T3	4		T33	3		T43	1
auto[1]	values[5]	valids[0x0]	372	1			T3	1		T89	1		T28	1
auto[1]	values[5]	valids[0x1]	262	1			T3	1		T33	6		T43	1
auto[1]	values[6]	valids[0x0]	314	1			T3	1		T33	4		T28	3
auto[1]	values[6]	valids[0x1]	267	1			T3	1		T33	2		T28	7
auto[1]	values[7]	valids[0x0]	392	1			T3	3		T34	1		T33	3
auto[1]	values[7]	valids[0x1]	246	1			T3	5		T33	1		T28	2
auto[1]	values[8]	valids[0x0]	2342	1			T3	16		T11	5		T33	13
auto[1]	values[8]	valids[0x1]	1703	1			T3	9		T34	1		T33	13