Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2955035

1

T1

1

T2

9712

T3

7270

auto[1]

21877

1

T2

170

T3

13

T7

104

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

876192

1

T1

1

T2

46

T3

43

auto[1]

2100720

1

T2

9836

T3

7240

T7

13690

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	555412	1			T1	1		T2	2011		T3	1977
auto[524288:1048575]	300787	1			T2	1575		T3	927		T7	5
auto[1048576:1572863]	358105	1			T2	387		T10	590		T34	1
auto[1572864:2097151]	317996	1			T2	272		T3	2716		T7	4287
auto[2097152:2621439]	383931	1			T2	25		T3	1		T4	2
auto[2621440:3145727]	338488	1			T2	514		T3	767		T7	1
auto[3145728:3670015]	324375	1			T2	2402		T3	750		T7	3322
auto[3670016:4194303]	397818	1			T2	2696		T3	145		T4	64

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2120877

1

T1

1

T2

9871

T3

7282

auto[1]

856035

1

T2

11

T3

1

T4

141

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2493860

1

T1

1

T2

6920

T3

2493

auto[1]

483052

1

T2

2962

T3

4790

T7

2319

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	203142	1			T1	1		T2	2		T3	3
auto[0]	auto[0]	auto[0:524287]	auto[1]	282753	1			T2	2005		T3	1		T7	5650
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	84285	1			T3	2		T7	2		T11	1276
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	171688	1			T3	922		T7	3		T33	569
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	115948	1			T2	1		T10	590		T34	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	194053	1			T2	128		T33	128		T28	257
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	66748	1			T2	4		T3	4		T7	7
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	183074	1			T2	258		T3	1038		T7	2047
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	91280	1			T2	2		T3	1		T4	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	224758	1			T2	1		T7	256		T33	2374
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	82923	1			T2	2		T3	11		T11	1437
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	184742	1			T2	512		T3	497		T28	614
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	97780	1			T2	12		T3	1		T7	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	152779	1			T2	1131		T7	3320		T33	256
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	123882	1			T2	3		T3	2		T4	64
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	215852	1			T2	2692		T3	1		T33	2203
auto[0]	auto[1]	auto[0:524287]	auto[0]	2373	1			T2	2		T3	3		T7	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	63627	1			T2	2		T3	1969		T7	128
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	393	1			T2	2		T29	2		T31	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	41978	1			T2	1573		T29	256		T31	258
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	215	1			T2	2		T28	1		T31	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	45493	1			T2	256		T159	2339		T165	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	3189	1			T7	2		T33	5		T28	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	62034	1			T3	1672		T7	2184		T33	1024
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	273	1			T7	2		T28	3		T31	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	65226	1			T28	956		T31	1		T43	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	277	1			T7	1		T28	1		T43	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	67882	1			T3	256		T28	512		T43	2185
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	979	1			T2	1		T3	5		T7	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	70286	1			T2	1120		T3	741		T159	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	404	1			T2	1		T3	2		T31	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	54719	1			T3	139		T31	1		T159	2223
auto[1]	auto[0]	auto[0:524287]	auto[0]	269	1			T3	1		T7	1		T28	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2851	1			T7	56		T28	1		T31	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	180	1			T3	2		T33	1		T28	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1761	1			T3	1		T33	7		T28	50
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	202	1			T28	1		T29	1		T31	7
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1934	1			T28	26		T29	3		T31	41
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	189	1			T2	2		T3	1		T7	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2208	1			T2	8		T3	1		T7	46
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	192	1			T2	1		T31	2		T14	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1794	1			T2	21		T31	2		T14	7
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	215	1			T3	2		T28	2		T31	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2053	1			T3	1		T28	73		T31	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	198	1			T2	8		T28	1		T29	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1865	1			T2	127		T28	26		T29	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	205	1			T3	1		T33	1		T28	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2057	1			T33	8		T28	26		T29	4
auto[1]	auto[1]	auto[0:524287]	auto[0]	53	1			T14	5		T41	1		T230	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	344	1			T14	8		T41	4		T230	6
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	61	1			T43	2		T14	2		T159	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	441	1			T43	47		T14	4		T159	8
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	35	1			T165	1		T127	1		T231	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	225	1			T165	1		T127	4		T231	15
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	55	1			T31	1		T15	6		T19	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	499	1			T15	6		T19	9		T232	7
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	57	1			T31	1		T43	1		T159	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	351	1			T43	2		T159	35		T127	22
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	63	1			T43	1		T15	3		T127	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	333	1			T43	2		T15	1		T127	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	62	1			T2	1		T3	2		T159	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	426	1			T2	2		T3	1		T16	16
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	65	1			T31	1		T159	3		T15	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	634	1			T159	22		T15	1		T16	9

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1625903	1			T1	1		T2	6744		T3	2483
auto[0]	auto[0]	auto[1]	849784	1			T2	9		T4	141		T10	7315
auto[0]	auto[1]	auto[0]	473455	1			T2	2959		T3	4787		T7	2319
auto[0]	auto[1]	auto[1]	5893	1			T43	1		T41	1		T91	2
auto[1]	auto[0]	auto[0]	17892	1			T2	165		T3	10		T7	104
auto[1]	auto[0]	auto[1]	281	1			T2	2		T31	3		T43	2
auto[1]	auto[1]	auto[0]	3627	1			T2	3		T3	2		T31	3
auto[1]	auto[1]	auto[1]	77	1			T3	1		T159	3		T165	1