Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14818

1

T2

80

T6

16

T7

129

auto[1]

11555

1

T1

20

T2

230

T7

115

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3437	1			T1	20		T2	20		T88	2
values[1]	2909	1			T2	131		T184	20		T39	20
values[2]	3246	1			T2	27		T6	16		T7	20
values[3]	3469	1			T2	90		T9	20		T42	8
values[4]	3622	1			T7	87		T37	20		T29	20
values[5]	3265	1			T2	42		T7	117		T113	12
values[6]	2659	1			T7	20		T8	18		T114	8
values[7]	3766	1			T29	33		T30	20		T31	47

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3652	1			T2	42		T7	40		T114	8
values[1]	2813	1			T37	20		T29	32		T31	49
values[2]	3311	1			T2	70		T7	77		T9	20
values[3]	3370	1			T2	86		T10	6		T29	33
values[4]	3549	1			T7	107		T42	8		T113	12
values[5]	3658	1			T1	20		T2	92		T6	16
values[6]	2659	1			T29	37		T30	20		T31	24
values[7]	3361	1			T2	20		T8	18		T29	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	249	1			T207	6		T196	14		T167	34
auto[0]	values[0]	values[1]	287	1			T166	13		T168	53		T228	13
auto[0]	values[0]	values[2]	381	1			T88	2		T15	9		T58	2
auto[0]	values[0]	values[3]	281	1			T233	29		T192	6		T166	16
auto[0]	values[0]	values[4]	128	1			T41	8		T132	34		T81	10
auto[0]	values[0]	values[5]	199	1			T38	10		T127	11		T92	18
auto[0]	values[0]	values[6]	182	1			T81	9		T17	10		T166	9
auto[0]	values[0]	values[7]	164	1			T2	16		T127	12		T166	12
auto[0]	values[1]	values[0]	334	1			T15	13		T217	6		T151	87
auto[0]	values[1]	values[1]	166	1			T40	43		T234	6		T185	9
auto[0]	values[1]	values[2]	199	1			T132	7		T168	10		T235	8
auto[0]	values[1]	values[3]	180	1			T2	9		T236	2		T182	12
auto[0]	values[1]	values[4]	333	1			T17	172		T217	12		T45	20
auto[0]	values[1]	values[5]	202	1			T2	11		T168	10		T167	19
auto[0]	values[1]	values[6]	113	1			T221	48		T237	4		T238	10
auto[0]	values[1]	values[7]	154	1			T40	13		T151	59		T210	13
auto[0]	values[2]	values[0]	186	1			T41	15		T132	17		T190	9
auto[0]	values[2]	values[1]	298	1			T15	12		T166	12		T53	56
auto[0]	values[2]	values[2]	210	1			T81	9		T181	14		T190	8
auto[0]	values[2]	values[3]	158	1			T10	6		T41	9		T91	20
auto[0]	values[2]	values[4]	405	1			T7	7		T127	11		T239	4
auto[0]	values[2]	values[5]	221	1			T2	18		T6	16		T132	13
auto[0]	values[2]	values[6]	219	1			T29	33		T127	8		T240	2
auto[0]	values[2]	values[7]	156	1			T17	10		T166	23		T190	10
auto[0]	values[3]	values[0]	383	1			T31	7		T41	9		T127	24
auto[0]	values[3]	values[1]	218	1			T17	14		T241	6		T209	12
auto[0]	values[3]	values[2]	253	1			T2	8		T9	20		T206	8
auto[0]	values[3]	values[3]	270	1			T242	4		T166	14		T243	2
auto[0]	values[3]	values[4]	140	1			T127	9		T244	10		T151	14
auto[0]	values[3]	values[5]	201	1			T2	7		T17	17		T45	20
auto[0]	values[3]	values[6]	392	1			T31	15		T127	37		T81	12
auto[0]	values[3]	values[7]	142	1			T29	10		T162	4		T15	8
auto[0]	values[4]	values[0]	407	1			T31	11		T41	12		T17	20
auto[0]	values[4]	values[1]	171	1			T31	19		T228	8		T245	10
auto[0]	values[4]	values[2]	136	1			T41	12		T81	12		T228	9
auto[0]	values[4]	values[3]	226	1			T31	14		T216	12		T132	17
auto[0]	values[4]	values[4]	207	1			T7	26		T95	6		T31	11
auto[0]	values[4]	values[5]	385	1			T29	11		T31	15		T131	4
auto[0]	values[4]	values[6]	222	1			T189	6		T151	13		T182	14
auto[0]	values[4]	values[7]	155	1			T81	13		T228	11		T213	4
auto[0]	values[5]	values[0]	140	1			T2	11		T7	10		T31	11
auto[0]	values[5]	values[1]	159	1			T29	22		T81	12		T246	12
auto[0]	values[5]	values[2]	233	1			T7	70		T168	14		T151	31
auto[0]	values[5]	values[3]	263	1			T166	13		T191	16		T196	12
auto[0]	values[5]	values[4]	434	1			T113	12		T247	2		T31	10
auto[0]	values[5]	values[5]	245	1			T7	9		T81	43		T196	10
auto[0]	values[5]	values[6]	118	1			T15	14		T127	25		T202	14
auto[0]	values[5]	values[7]	315	1			T167	7		T190	9		T151	10
auto[0]	values[6]	values[0]	220	1			T7	7		T114	8		T15	19
auto[0]	values[6]	values[1]	91	1			T40	16		T166	26		T248	4
auto[0]	values[6]	values[2]	116	1			T15	14		T192	18		T249	6
auto[0]	values[6]	values[3]	223	1			T31	11		T81	67		T168	5
auto[0]	values[6]	values[4]	185	1			T29	11		T160	4		T15	9
auto[0]	values[6]	values[5]	173	1			T166	22		T209	7		T45	35
auto[0]	values[6]	values[6]	106	1			T127	10		T250	6		T251	22
auto[0]	values[6]	values[7]	474	1			T8	18		T31	10		T252	2
auto[0]	values[7]	values[0]	102	1			T166	11		T49	8		T253	10
auto[0]	values[7]	values[1]	378	1			T31	18		T15	7		T132	16
auto[0]	values[7]	values[2]	280	1			T15	11		T81	10		T205	16
auto[0]	values[7]	values[3]	415	1			T29	9		T81	9		T254	45
auto[0]	values[7]	values[4]	195	1			T31	15		T81	30		T255	10
auto[0]	values[7]	values[5]	288	1			T41	16		T168	7		T217	10
auto[0]	values[7]	values[6]	173	1			T30	13		T41	12		T132	7
auto[0]	values[7]	values[7]	179	1			T228	10		T94	13		T215	13
auto[1]	values[0]	values[0]	213	1			T207	14		T196	6		T167	4
auto[1]	values[0]	values[1]	140	1			T166	7		T168	13		T228	8
auto[1]	values[0]	values[2]	270	1			T15	15		T190	11		T256	10
auto[1]	values[0]	values[3]	68	1			T198	4		T192	14		T166	4
auto[1]	values[0]	values[4]	110	1			T41	40		T132	7		T81	10
auto[1]	values[0]	values[5]	255	1			T1	20		T127	9		T81	4
auto[1]	values[0]	values[6]	151	1			T81	11		T17	16		T166	11
auto[1]	values[0]	values[7]	359	1			T2	4		T127	8		T201	20
auto[1]	values[1]	values[0]	179	1			T15	9		T217	14		T151	8
auto[1]	values[1]	values[1]	51	1			T40	9		T185	11		T212	9
auto[1]	values[1]	values[2]	213	1			T132	13		T168	10		T167	10
auto[1]	values[1]	values[3]	163	1			T2	77		T182	10		T185	7
auto[1]	values[1]	values[4]	119	1			T17	6		T217	18		T45	15
auto[1]	values[1]	values[5]	324	1			T2	34		T184	20		T39	20
auto[1]	values[1]	values[6]	104	1			T221	69		T238	10		T257	4
auto[1]	values[1]	values[7]	75	1			T40	7		T151	8		T210	10
auto[1]	values[2]	values[0]	178	1			T41	5		T132	5		T190	11
auto[1]	values[2]	values[1]	156	1			T15	10		T166	8		T45	8
auto[1]	values[2]	values[2]	105	1			T81	18		T190	12		T179	8
auto[1]	values[2]	values[3]	156	1			T41	11		T127	20		T258	7
auto[1]	values[2]	values[4]	327	1			T7	13		T127	9		T151	10
auto[1]	values[2]	values[5]	180	1			T2	9		T132	7		T17	11
auto[1]	values[2]	values[6]	182	1			T29	4		T127	12		T196	10
auto[1]	values[2]	values[7]	109	1			T17	36		T166	5		T190	10
auto[1]	values[3]	values[0]	190	1			T31	19		T41	11		T127	17
auto[1]	values[3]	values[1]	184	1			T17	12		T209	8		T202	6
auto[1]	values[3]	values[2]	188	1			T2	62		T127	8		T17	59
auto[1]	values[3]	values[3]	263	1			T166	82		T209	6		T215	7
auto[1]	values[3]	values[4]	180	1			T42	8		T127	19		T151	10
auto[1]	values[3]	values[5]	219	1			T2	13		T17	7		T45	5
auto[1]	values[3]	values[6]	117	1			T31	9		T127	6		T81	8
auto[1]	values[3]	values[7]	129	1			T29	10		T15	12		T259	4
auto[1]	values[4]	values[0]	266	1			T31	9		T41	8		T17	11
auto[1]	values[4]	values[1]	165	1			T37	20		T31	5		T228	12
auto[1]	values[4]	values[2]	405	1			T41	48		T81	8		T228	16
auto[1]	values[4]	values[3]	91	1			T31	6		T132	3		T196	13
auto[1]	values[4]	values[4]	308	1			T7	61		T31	56		T41	8
auto[1]	values[4]	values[5]	174	1			T29	9		T31	5		T17	11
auto[1]	values[4]	values[6]	145	1			T151	7		T182	6		T221	7
auto[1]	values[4]	values[7]	159	1			T81	7		T228	9		T153	11
auto[1]	values[5]	values[0]	291	1			T2	31		T7	10		T31	49
auto[1]	values[5]	values[1]	83	1			T29	10		T81	17		T190	15
auto[1]	values[5]	values[2]	91	1			T7	7		T168	15		T203	14
auto[1]	values[5]	values[3]	89	1			T166	7		T196	10		T215	12
auto[1]	values[5]	values[4]	192	1			T31	34		T41	21		T127	9
auto[1]	values[5]	values[5]	164	1			T7	11		T81	13		T196	16
auto[1]	values[5]	values[6]	127	1			T15	7		T127	22		T202	13
auto[1]	values[5]	values[7]	321	1			T167	79		T190	11		T151	10
auto[1]	values[6]	values[0]	248	1			T7	13		T15	21		T132	11
auto[1]	values[6]	values[1]	31	1			T40	10		T166	4		T221	8
auto[1]	values[6]	values[2]	83	1			T15	8		T192	2		T45	11
auto[1]	values[6]	values[3]	170	1			T31	11		T81	9		T168	30
auto[1]	values[6]	values[4]	132	1			T29	9		T15	13		T207	12
auto[1]	values[6]	values[5]	189	1			T166	102		T209	13		T45	8
auto[1]	values[6]	values[6]	62	1			T127	10		T260	10		T261	8
auto[1]	values[6]	values[7]	156	1			T31	10		T41	16		T168	10
auto[1]	values[7]	values[0]	66	1			T166	9		T262	12		T49	12
auto[1]	values[7]	values[1]	235	1			T31	7		T15	15		T132	9
auto[1]	values[7]	values[2]	148	1			T15	9		T81	11		T215	7
auto[1]	values[7]	values[3]	354	1			T29	24		T81	78		T168	5
auto[1]	values[7]	values[4]	154	1			T31	7		T81	10		T168	54
auto[1]	values[7]	values[5]	239	1			T41	12		T168	81		T217	10
auto[1]	values[7]	values[6]	246	1			T30	7		T41	8		T132	13
auto[1]	values[7]	values[7]	314	1			T228	10		T94	11		T215	7