Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2657286	1			T1	1		T2	2842		T3	14206
all_pins[1]	2657286	1			T1	1		T2	2842		T3	14206
all_pins[2]	2657286	1			T1	1		T2	2842		T3	14206
all_pins[3]	2657286	1			T1	1		T2	2842		T3	14206
all_pins[4]	2657286	1			T1	1		T2	2842		T3	14206
all_pins[5]	2657286	1			T1	1		T2	2842		T3	14206
all_pins[6]	2657286	1			T1	1		T2	2842		T3	14206
all_pins[7]	2657286	1			T1	1		T2	2842		T3	14206

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21188343	1			T1	8		T2	22736		T3	113639
values[0x1]	69945	1			T3	9		T14	999		T15	446
transitions[0x0=>0x1]	68388	1			T3	8		T14	998		T15	390
transitions[0x1=>0x0]	68398	1			T3	8		T14	998		T15	390

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2656530	1			T1	1		T2	2842		T3	14206
all_pins[0]	values[0x1]	756	1			T14	2		T15	166		T16	58
all_pins[0]	transitions[0x0=>0x1]	484	1			T14	2		T15	166		T16	58
all_pins[0]	transitions[0x1=>0x0]	650	1			T3	4		T14	277		T15	144
all_pins[1]	values[0x0]	2656364	1			T1	1		T2	2842		T3	14202
all_pins[1]	values[0x1]	922	1			T3	4		T14	277		T15	144
all_pins[1]	transitions[0x0=>0x1]	744	1			T3	3		T14	277		T15	88
all_pins[1]	transitions[0x1=>0x0]	199	1			T15	71		T16	16		T19	2
all_pins[2]	values[0x0]	2656909	1			T1	1		T2	2842		T3	14205
all_pins[2]	values[0x1]	377	1			T3	1		T15	127		T16	18
all_pins[2]	transitions[0x0=>0x1]	336	1			T3	1		T15	127		T16	18
all_pins[2]	transitions[0x1=>0x0]	140	1			T14	5		T19	2		T21	1
all_pins[3]	values[0x0]	2657105	1			T1	1		T2	2842		T3	14206
all_pins[3]	values[0x1]	181	1			T14	5		T19	2		T21	3
all_pins[3]	transitions[0x0=>0x1]	141	1			T14	5		T19	2		T21	3
all_pins[3]	transitions[0x1=>0x0]	148	1			T15	5		T16	6		T19	1
all_pins[4]	values[0x0]	2657098	1			T1	1		T2	2842		T3	14206
all_pins[4]	values[0x1]	188	1			T15	5		T16	6		T19	1
all_pins[4]	transitions[0x0=>0x1]	157	1			T15	5		T16	5		T19	1
all_pins[4]	transitions[0x1=>0x0]	1972	1			T3	1		T14	709		T15	3
all_pins[5]	values[0x0]	2655283	1			T1	1		T2	2842		T3	14205
all_pins[5]	values[0x1]	2003	1			T3	1		T14	709		T15	3
all_pins[5]	transitions[0x0=>0x1]	1080	1			T3	1		T14	709		T15	3
all_pins[5]	transitions[0x1=>0x0]	64445	1			T14	3		T15	1		T19	1566
all_pins[6]	values[0x0]	2591918	1			T1	1		T2	2842		T3	14206
all_pins[6]	values[0x1]	65368	1			T14	3		T15	1		T19	1566
all_pins[6]	transitions[0x0=>0x1]	65336	1			T14	3		T15	1		T19	1566
all_pins[6]	transitions[0x1=>0x0]	118	1			T3	3		T14	3		T16	3
all_pins[7]	values[0x0]	2657136	1			T1	1		T2	2842		T3	14203
all_pins[7]	values[0x1]	150	1			T3	3		T14	3		T16	3
all_pins[7]	transitions[0x0=>0x1]	110	1			T3	3		T14	2		T16	3
all_pins[7]	transitions[0x1=>0x0]	726	1			T14	1		T15	166		T16	58