Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	333	1			T2	3		T7	3		T29	3
auto[ReadAddrCrossIntoMailbox]	269	1			T2	6		T7	1		T29	3
auto[ReadAddrCrossOutOfMailbox]	246	1			T2	1		T7	2		T29	2
auto[ReadAddrCrossAllMailbox]	167	1			T7	1		T15	6		T41	3
auto[ReadAddrOutsideMailbox]	3010	1			T2	18		T7	20		T8	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2009

1

T2

9

T7

15

T8

3

auto[1]

2016

1

T2

19

T7

12

T8

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	664	1			T2	4		T7	5		T113	12
read_ops[0x0b]	708	1			T2	3		T7	5		T8	2
read_ops[0x3b]	636	1			T2	5		T7	6		T29	2
read_ops[0x6b]	716	1			T2	1		T7	6		T8	4
read_ops[0xbb]	631	1			T2	4		T7	2		T29	2
read_ops[0xeb]	670	1			T2	11		T7	3		T29	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T30	1		T81	1		T213	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	20	1			T41	1		T132	1		T213	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T2	1		T7	1		T15	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T2	1		T31	1		T192	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T30	1		T41	3		T127	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T2	1		T132	1		T59	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T81	1		T207	1		T166	3
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T15	1		T41	1		T81	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	244	1			T7	4		T113	6		T29	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	245	1			T2	1		T113	6		T29	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T31	2		T132	2		T168	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T31	1		T41	2		T127	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T2	2		T31	2		T15	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T31	1		T15	1		T127	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T29	1		T15	1		T41	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T31	1		T41	1		T127	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T17	1		T166	1		T240	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T15	1		T81	1		T240	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	263	1			T7	5		T8	1		T9	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	250	1			T2	1		T8	1		T9	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T41	2		T127	1		T17	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T7	1		T15	1		T228	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T2	1		T29	1		T41	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	10	1			T255	1		T196	1		T190	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T41	4		T127	1		T166	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T7	1		T15	1		T41	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T15	2		T127	1		T192	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T7	1		T15	1		T132	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	240	1			T2	1		T29	1		T31	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	249	1			T2	3		T7	3		T31	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T252	1		T41	1		T132	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T7	1		T31	1		T252	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T41	1		T132	1		T208	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T29	2		T15	1		T41	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T127	1		T132	1		T81	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T31	1		T81	1		T196	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T132	1		T81	1		T182	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T167	1		T217	1		T228	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T2	1		T7	4		T8	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	274	1			T7	1		T8	2		T38	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T29	1		T31	2		T15	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T2	2		T7	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T127	1		T132	3		T17	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T31	1		T17	1		T217	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T31	1		T15	2		T127	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T41	1		T127	2		T17	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T196	1		T45	1		T202	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T166	2		T151	1		T202	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	213	1			T2	1		T29	1		T30	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	249	1			T2	1		T7	1		T31	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T29	2		T132	2		T166	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T2	1		T30	2		T41	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T81	1		T166	2		T168	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T2	1		T15	1		T127	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T7	1		T29	1		T127	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T15	1		T217	1		T94	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T15	1		T41	1		T81	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	7	1			T41	1		T132	1		T49	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T2	2		T29	1		T31	7
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	249	1			T2	7		T7	2		T29	2