Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3332	1			T2	87		T113	12		T252	2
values[1]	3381	1			T2	106		T7	87		T9	20
values[2]	2654	1			T2	20		T10	6		T31	44
values[3]	3246	1			T2	27		T6	16		T7	20
values[4]	3886	1			T7	20		T37	20		T88	2
values[5]	3439	1			T2	70		T7	20		T30	20
values[6]	3401	1			T1	20		T7	77		T8	18
values[7]	3034	1			T7	20		T42	8		T184	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2952	1			T2	27		T7	40		T10	6
values[1]	3585	1			T2	65		T247	2		T31	90
values[2]	2834	1			T9	20		T184	20		T40	52
values[3]	3031	1			T2	70		T8	18		T114	8
values[4]	3692	1			T1	20		T7	20		T29	32
values[5]	3390	1			T2	128		T7	20		T42	8
values[6]	3556	1			T2	20		T6	16		T7	77
values[7]	3333	1			T7	87		T37	20		T88	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25775

1

T1

14

T2

299

T6

16

auto[1]

598

1

T1

6

T2

11

T7

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	356	1			T127	20		T81	20		T250	6
auto[0]	values[0]	values[1]	421	1			T2	42		T15	19		T81	20
auto[0]	values[0]	values[2]	258	1			T252	2		T166	19		T190	20
auto[0]	values[0]	values[3]	570	1			T15	19		T94	24		T151	20
auto[0]	values[0]	values[4]	410	1			T41	46		T59	4		T209	21
auto[0]	values[0]	values[5]	613	1			T2	40		T113	12		T41	49
auto[0]	values[0]	values[6]	218	1			T127	21		T196	20		T217	28
auto[0]	values[0]	values[7]	394	1			T132	20		T168	109		T190	20
auto[0]	values[1]	values[0]	274	1			T7	19		T38	10		T31	25
auto[0]	values[1]	values[1]	495	1			T2	20		T31	24		T207	53
auto[0]	values[1]	values[2]	425	1			T9	20		T15	22		T259	4
auto[0]	values[1]	values[3]	331	1			T127	20		T81	40		T190	18
auto[0]	values[1]	values[4]	370	1			T15	24		T41	20		T166	17
auto[0]	values[1]	values[5]	611	1			T2	81		T216	12		T127	27
auto[0]	values[1]	values[6]	271	1			T160	4		T81	20		T166	20
auto[0]	values[1]	values[7]	533	1			T7	65		T29	20		T132	35
auto[0]	values[2]	values[0]	529	1			T10	6		T15	20		T41	20
auto[0]	values[2]	values[1]	278	1			T31	20		T127	20		T196	20
auto[0]	values[2]	values[2]	268	1			T127	19		T132	41		T81	27
auto[0]	values[2]	values[3]	248	1			T132	23		T81	27		T228	22
auto[0]	values[2]	values[4]	276	1			T31	22		T58	2		T256	6
auto[0]	values[2]	values[5]	235	1			T127	19		T166	20		T196	25
auto[0]	values[2]	values[6]	401	1			T2	20		T168	131		T202	20
auto[0]	values[2]	values[7]	334	1			T132	20		T181	14		T263	10
auto[0]	values[3]	values[0]	261	1			T2	27		T7	19		T29	33
auto[0]	values[3]	values[1]	550	1			T41	19		T81	19		T17	22
auto[0]	values[3]	values[2]	463	1			T17	24		T168	39		T248	4
auto[0]	values[3]	values[3]	470	1			T29	37		T193	8		T94	20
auto[0]	values[3]	values[4]	447	1			T167	84		T215	20		T264	14
auto[0]	values[3]	values[5]	369	1			T189	6		T209	20		T251	22
auto[0]	values[3]	values[6]	322	1			T6	16		T31	127		T81	21
auto[0]	values[3]	values[7]	304	1			T29	20		T45	22		T151	33
auto[0]	values[4]	values[0]	515	1			T127	28		T17	46		T168	87
auto[0]	values[4]	values[1]	517	1			T206	8		T41	27		T192	20
auto[0]	values[4]	values[2]	335	1			T221	77		T265	8		T266	10
auto[0]	values[4]	values[3]	349	1			T114	8		T198	4		T91	20
auto[0]	values[4]	values[4]	814	1			T29	28		T41	60		T17	248
auto[0]	values[4]	values[5]	466	1			T7	20		T233	29		T217	20
auto[0]	values[4]	values[6]	452	1			T31	44		T192	20		T168	19
auto[0]	values[4]	values[7]	364	1			T37	18		T88	2		T40	20
auto[0]	values[5]	values[0]	335	1			T166	30		T241	6		T179	20
auto[0]	values[5]	values[1]	359	1			T15	20		T81	19		T209	31
auto[0]	values[5]	values[2]	265	1			T40	52		T15	20		T166	19
auto[0]	values[5]	values[3]	531	1			T2	69		T166	27		T211	22
auto[0]	values[5]	values[4]	423	1			T30	20		T31	20		T127	18
auto[0]	values[5]	values[5]	334	1			T132	20		T17	19		T45	28
auto[0]	values[5]	values[6]	750	1			T166	93		T215	26		T221	40
auto[0]	values[5]	values[7]	373	1			T7	19		T254	45		T190	27
auto[0]	values[6]	values[0]	268	1			T15	20		T267	18		T228	19
auto[0]	values[6]	values[1]	519	1			T247	2		T31	44		T40	25
auto[0]	values[6]	values[2]	486	1			T41	45		T132	37		T166	20
auto[0]	values[6]	values[3]	201	1			T8	18		T81	24		T17	50
auto[0]	values[6]	values[4]	398	1			T1	14		T228	20		T45	48
auto[0]	values[6]	values[5]	334	1			T31	19		T158	4		T127	20
auto[0]	values[6]	values[6]	684	1			T7	77		T39	16		T15	20
auto[0]	values[6]	values[7]	437	1			T41	19		T131	4		T196	47
auto[0]	values[7]	values[0]	328	1			T45	21		T268	14		T269	22
auto[0]	values[7]	values[1]	354	1			T132	20		T81	87		T208	6
auto[0]	values[7]	values[2]	285	1			T184	20		T127	69		T242	4
auto[0]	values[7]	values[3]	260	1			T162	4		T236	2		T151	20
auto[0]	values[7]	values[4]	475	1			T7	19		T31	20		T41	20
auto[0]	values[7]	values[5]	348	1			T42	8		T15	43		T167	36
auto[0]	values[7]	values[6]	388	1			T201	20		T168	29		T209	20
auto[0]	values[7]	values[7]	523	1			T29	20		T31	25		T222	4
auto[1]	values[0]	values[0]	13	1			T215	2		T212	2		T270	1
auto[1]	values[0]	values[1]	19	1			T2	3		T15	2		T196	1
auto[1]	values[0]	values[2]	4	1			T166	1		T49	3		-	-
auto[1]	values[0]	values[3]	16	1			T15	1		T221	2		T49	8
auto[1]	values[0]	values[4]	11	1			T41	2		T209	1		T151	1
auto[1]	values[0]	values[5]	13	1			T2	2		T271	3		T272	3
auto[1]	values[0]	values[6]	5	1			T217	2		T273	2		T274	1
auto[1]	values[0]	values[7]	11	1			T168	2		T275	2		T273	3
auto[1]	values[1]	values[0]	9	1			T7	1		T31	1		T41	1
auto[1]	values[1]	values[1]	9	1			T207	1		T182	1		T276	2
auto[1]	values[1]	values[2]	4	1			T217	1		T151	3		-	-
auto[1]	values[1]	values[3]	9	1			T190	2		T209	1		T194	1
auto[1]	values[1]	values[4]	9	1			T166	3		T217	3		T277	1
auto[1]	values[1]	values[5]	15	1			T2	5		T229	2		T202	3
auto[1]	values[1]	values[6]	5	1			T278	2		T257	1		T279	2
auto[1]	values[1]	values[7]	11	1			T7	2		T132	1		T219	2
auto[1]	values[2]	values[0]	18	1			T15	2		T45	3		T151	3
auto[1]	values[2]	values[1]	4	1			T31	2		T280	1		T281	1
auto[1]	values[2]	values[2]	12	1			T127	1		T81	2		T282	5
auto[1]	values[2]	values[3]	10	1			T132	2		T228	3		T203	2
auto[1]	values[2]	values[4]	7	1			T256	4		T283	3		-	-
auto[1]	values[2]	values[5]	6	1			T127	1		T228	1		T190	2
auto[1]	values[2]	values[6]	13	1			T221	3		T226	3		T49	1
auto[1]	values[2]	values[7]	15	1			T132	2		T284	2		T188	2
auto[1]	values[3]	values[0]	7	1			T7	1		T215	5		T202	1
auto[1]	values[3]	values[1]	15	1			T41	1		T81	1		T17	3
auto[1]	values[3]	values[2]	4	1			T168	1		T45	2		T188	1
auto[1]	values[3]	values[3]	11	1			T151	1		T285	2		T273	1
auto[1]	values[3]	values[4]	9	1			T167	2		T278	1		T257	1
auto[1]	values[3]	values[5]	2	1			T94	1		T49	1		-	-
auto[1]	values[3]	values[6]	9	1			T182	6		T187	1		T49	2
auto[1]	values[3]	values[7]	3	1			T45	1		T151	1		T286	1
auto[1]	values[4]	values[0]	6	1			T127	1		T168	1		T151	1
auto[1]	values[4]	values[1]	11	1			T41	1		T287	2		T257	1
auto[1]	values[4]	values[2]	7	1			T212	4		T138	1		T288	2
auto[1]	values[4]	values[3]	2	1			T289	2		-	-		-	-
auto[1]	values[4]	values[4]	17	1			T29	4		T290	4		T212	2
auto[1]	values[4]	values[5]	16	1			T190	2		T209	2		T151	5
auto[1]	values[4]	values[6]	10	1			T168	1		T151	1		T188	1
auto[1]	values[4]	values[7]	5	1			T37	2		T127	1		T81	1
auto[1]	values[5]	values[0]	11	1			T291	3		T292	2		T293	4
auto[1]	values[5]	values[1]	18	1			T81	1		T209	1		T151	1
auto[1]	values[5]	values[2]	3	1			T166	1		T294	1		T286	1
auto[1]	values[5]	values[3]	9	1			T2	1		T166	1		T215	2
auto[1]	values[5]	values[4]	8	1			T127	2		T182	1		T295	2
auto[1]	values[5]	values[5]	6	1			T17	1		T45	1		T238	1
auto[1]	values[5]	values[6]	6	1			T166	3		T294	1		T212	1
auto[1]	values[5]	values[7]	8	1			T7	1		T292	3		T296	4
auto[1]	values[6]	values[0]	11	1			T15	2		T267	4		T228	1
auto[1]	values[6]	values[1]	12	1			T40	1		T41	1		T153	1
auto[1]	values[6]	values[2]	9	1			T132	3		T182	2		T210	1
auto[1]	values[6]	values[3]	8	1			T81	3		T17	2		T297	2
auto[1]	values[6]	values[4]	9	1			T1	6		T151	2		T49	1
auto[1]	values[6]	values[5]	7	1			T31	1		T17	1		T298	1
auto[1]	values[6]	values[6]	10	1			T39	4		T45	1		T49	1
auto[1]	values[6]	values[7]	8	1			T41	1		T196	1		T262	2
auto[1]	values[7]	values[0]	11	1			T269	2		T295	3		T299	2
auto[1]	values[7]	values[1]	4	1			T300	1		T301	3		-	-
auto[1]	values[7]	values[2]	6	1			T127	1		T215	1		T210	1
auto[1]	values[7]	values[3]	6	1			T138	3		T288	1		T280	1
auto[1]	values[7]	values[4]	9	1			T7	1		T166	1		T217	1
auto[1]	values[7]	values[5]	15	1			T15	1		T167	2		T292	4
auto[1]	values[7]	values[6]	12	1			T202	3		T210	1		T188	1
auto[1]	values[7]	values[7]	10	1			T153	1		T185	1		T271	2