Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1991

1

T3

12

T12

7

T25

12

auto[1]

1919

1

T3

11

T12

2

T25

16

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2196

1

T3

23

T26

1

T27

11

auto[1]

1714

1

T12

9

T25

28

T27

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3086

1

T3

17

T12

9

T25

28

auto[1]

824

1

T3

6

T27

7

T29

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	811	1			T3	3		T12	2		T25	7
valid[1]	753	1			T3	9		T12	1		T25	2
valid[2]	744	1			T3	5		T25	5		T27	3
valid[3]	813	1			T3	4		T12	5		T25	5
valid[4]	789	1			T3	2		T12	1		T25	9

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	137	1			T27	1		T29	1		T30	2
auto[0]	auto[0]	valid[0]	auto[1]	177	1			T12	2		T25	4		T43	1
auto[0]	auto[0]	valid[1]	auto[0]	140	1			T3	5		T28	1		T29	3
auto[0]	auto[0]	valid[1]	auto[1]	159	1			T12	1		T27	1		T31	1
auto[0]	auto[0]	valid[2]	auto[0]	120	1			T3	2		T29	2		T44	2
auto[0]	auto[0]	valid[2]	auto[1]	151	1			T25	1		T27	1		T30	1
auto[0]	auto[0]	valid[3]	auto[0]	153	1			T3	2		T29	1		T14	3
auto[0]	auto[0]	valid[3]	auto[1]	186	1			T12	4		T25	3		T30	1
auto[0]	auto[0]	valid[4]	auto[0]	150	1			T26	1		T30	1		T14	1
auto[0]	auto[0]	valid[4]	auto[1]	180	1			T25	4		T85	1		T161	1
auto[0]	auto[1]	valid[0]	auto[0]	152	1			T3	1		T29	2		T30	1
auto[0]	auto[1]	valid[0]	auto[1]	173	1			T25	3		T27	1		T85	1
auto[0]	auto[1]	valid[1]	auto[0]	113	1			T3	3		T27	1		T29	4
auto[0]	auto[1]	valid[1]	auto[1]	175	1			T25	2		T27	2		T85	2
auto[0]	auto[1]	valid[2]	auto[0]	138	1			T3	2		T27	1		T29	2
auto[0]	auto[1]	valid[2]	auto[1]	171	1			T25	4		T43	1		T85	1
auto[0]	auto[1]	valid[3]	auto[0]	130	1			T29	1		T30	4		T43	1
auto[0]	auto[1]	valid[3]	auto[1]	156	1			T12	1		T25	2		T30	1
auto[0]	auto[1]	valid[4]	auto[0]	139	1			T3	2		T27	1		T29	2
auto[0]	auto[1]	valid[4]	auto[1]	186	1			T12	1		T25	5		T85	1
auto[1]	auto[0]	valid[0]	auto[0]	98	1			T3	1		T27	2		T14	2
auto[1]	auto[0]	valid[1]	auto[0]	82	1			T3	1		T27	2		T29	1
auto[1]	auto[0]	valid[2]	auto[0]	81	1			T29	2		T14	1		T15	2
auto[1]	auto[0]	valid[3]	auto[0]	106	1			T3	1		T29	2		T30	1
auto[1]	auto[0]	valid[4]	auto[0]	71	1			T14	1		T159	1		T165	1
auto[1]	auto[1]	valid[0]	auto[0]	74	1			T3	1		T31	2		T44	1
auto[1]	auto[1]	valid[1]	auto[0]	84	1			T29	1		T31	1		T44	1
auto[1]	auto[1]	valid[2]	auto[0]	83	1			T3	1		T27	1		T30	1
auto[1]	auto[1]	valid[3]	auto[0]	82	1			T3	1		T27	2		T30	1
auto[1]	auto[1]	valid[4]	auto[0]	63	1			T165	2		T15	1		T134	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal