Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	743	1			T3	4		T14	10		T15	15
all_values[1]	743	1			T3	4		T14	10		T15	15
all_values[2]	743	1			T3	4		T14	10		T15	15
all_values[3]	743	1			T3	4		T14	10		T15	15
all_values[4]	743	1			T3	4		T14	10		T15	15
all_values[5]	743	1			T3	4		T14	10		T15	15
all_values[6]	743	1			T3	4		T14	10		T15	15
all_values[7]	743	1			T3	4		T14	10		T15	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3153

1

T3

23

T14

45

T15

82

auto[1]

2791

1

T3

9

T14

35

T15

38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2341

1

T3

16

T14

31

T15

52

auto[1]

3603

1

T3

16

T14

49

T15

68

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3358

1

T3

21

T14

43

T15

71

auto[1]

2586

1

T3

11

T14

37

T15

49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	141	1			T3	4		T15	2		T16	2
all_values[0]	auto[0]	auto[0]	auto[1]	73	1			T14	3		T15	3		T16	1
all_values[0]	auto[0]	auto[1]	auto[0]	127	1			T15	3		T16	2		T19	1
all_values[0]	auto[0]	auto[1]	auto[1]	64	1			T19	1		T21	1		T22	2
all_values[0]	auto[1]	auto[0]	auto[1]	180	1			T14	5		T15	5		T16	3
all_values[0]	auto[1]	auto[1]	auto[1]	158	1			T14	2		T15	2		T19	2
all_values[1]	auto[0]	auto[0]	auto[0]	135	1			T14	1		T15	2		T16	2
all_values[1]	auto[0]	auto[0]	auto[1]	73	1			T14	2		T15	3		T16	2
all_values[1]	auto[0]	auto[1]	auto[0]	134	1			T14	2		T19	2		T21	3
all_values[1]	auto[0]	auto[1]	auto[1]	75	1			T3	2		T15	5		T16	1
all_values[1]	auto[1]	auto[0]	auto[1]	179	1			T3	1		T14	3		T15	4
all_values[1]	auto[1]	auto[1]	auto[1]	147	1			T3	1		T14	2		T15	1
all_values[2]	auto[0]	auto[0]	auto[0]	145	1			T3	3		T14	3		T15	5
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T15	1		T19	1		T21	1
all_values[2]	auto[0]	auto[1]	auto[0]	132	1			T14	3		T15	4		T16	4
all_values[2]	auto[0]	auto[1]	auto[1]	58	1			T19	1		T22	3		T150	2
all_values[2]	auto[1]	auto[0]	auto[1]	165	1			T14	3		T15	4		T16	1
all_values[2]	auto[1]	auto[1]	auto[1]	160	1			T3	1		T14	1		T15	1
all_values[3]	auto[0]	auto[0]	auto[0]	144	1			T15	8		T19	4		T21	1
all_values[3]	auto[0]	auto[0]	auto[1]	74	1			T3	1		T14	2		T21	1
all_values[3]	auto[0]	auto[1]	auto[0]	129	1			T14	1		T15	3		T16	7
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T14	3		T19	1		T22	1
all_values[3]	auto[1]	auto[0]	auto[1]	158	1			T3	3		T14	2		T15	4
all_values[3]	auto[1]	auto[1]	auto[1]	158	1			T14	2		T19	2		T21	4
all_values[4]	auto[0]	auto[0]	auto[0]	166	1			T3	2		T14	6		T15	3
all_values[4]	auto[0]	auto[0]	auto[1]	60	1			T3	1		T15	1		T21	2
all_values[4]	auto[0]	auto[1]	auto[0]	114	1			T14	1		T15	2		T16	1
all_values[4]	auto[0]	auto[1]	auto[1]	88	1			T15	2		T16	3		T19	1
all_values[4]	auto[1]	auto[0]	auto[1]	167	1			T3	1		T14	3		T15	5
all_values[4]	auto[1]	auto[1]	auto[1]	148	1			T15	2		T16	2		T19	2
all_values[5]	auto[0]	auto[0]	auto[0]	231	1			T3	2		T14	2		T15	5
all_values[5]	auto[0]	auto[1]	auto[0]	201	1			T14	4		T16	1		T19	8
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T3	1		T14	2		T15	6
all_values[5]	auto[1]	auto[1]	auto[1]	137	1			T3	1		T14	2		T15	4
all_values[6]	auto[0]	auto[0]	auto[0]	151	1			T3	3		T14	1		T15	4
all_values[6]	auto[0]	auto[0]	auto[1]	69	1			T15	1		T16	1		T19	2
all_values[6]	auto[0]	auto[1]	auto[0]	117	1			T3	1		T14	2		T15	2
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T14	1		T21	1		T22	3
all_values[6]	auto[1]	auto[0]	auto[1]	187	1			T14	1		T15	6		T16	1
all_values[6]	auto[1]	auto[1]	auto[1]	138	1			T14	5		T15	2		T16	1
all_values[7]	auto[0]	auto[0]	auto[0]	159	1			T3	1		T14	3		T15	6
all_values[7]	auto[0]	auto[0]	auto[1]	68	1			T15	3		T19	2		T21	1
all_values[7]	auto[0]	auto[1]	auto[0]	115	1			T14	2		T15	3		T16	3
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T3	1		T14	1		T16	1
all_values[7]	auto[1]	auto[0]	auto[1]	171	1			T14	3		T15	1		T19	3
all_values[7]	auto[1]	auto[1]	auto[1]	159	1			T3	2		T14	1		T15	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal