Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54519

1

T3

696

T13

11

T26

2

auto[1]

17487

1

T12

9

T25

265

T27

117

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52181

1

T3

480

T12

9

T13

8

auto[1]

19825

1

T3

216

T13

3

T27

134

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	37102	1			T3	348		T12	9		T13	8
others[1]	6109	1			T3	60		T25	23		T27	44
others[2]	6239	1			T3	71		T25	27		T27	29
others[3]	6804	1			T3	67		T13	1		T25	26
interest[1]	3969	1			T3	35		T25	15		T27	15
interest[4]	24392	1			T3	209		T12	9		T13	5
interest[64]	11783	1			T3	115		T13	2		T25	39

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17702	1			T3	243		T13	6		T26	1
auto[0]	auto[0]	others[1]	2993	1			T3	42		T27	15		T28	1
auto[0]	auto[0]	others[2]	3032	1			T3	48		T27	12		T28	3
auto[0]	auto[0]	others[3]	3355	1			T3	56		T13	1		T27	12
auto[0]	auto[0]	interest[1]	1923	1			T3	23		T27	7		T28	2
auto[0]	auto[0]	interest[4]	11536	1			T3	140		T13	3		T26	1
auto[0]	auto[0]	interest[64]	5689	1			T3	68		T13	1		T26	1
auto[0]	auto[1]	others[0]	9153	1			T12	9		T25	135		T27	58
auto[0]	auto[1]	others[1]	1445	1			T25	23		T27	12		T30	7
auto[0]	auto[1]	others[2]	1524	1			T25	27		T27	11		T30	7
auto[0]	auto[1]	others[3]	1620	1			T25	26		T27	16		T30	7
auto[0]	auto[1]	interest[1]	922	1			T25	15		T27	4		T30	6
auto[0]	auto[1]	interest[4]	6211	1			T12	9		T25	84		T27	31
auto[0]	auto[1]	interest[64]	2823	1			T25	39		T27	16		T30	14
auto[1]	auto[0]	others[0]	10247	1			T3	105		T13	2		T27	68
auto[1]	auto[0]	others[1]	1671	1			T3	18		T27	17		T29	19
auto[1]	auto[0]	others[2]	1683	1			T3	23		T27	6		T29	14
auto[1]	auto[0]	others[3]	1829	1			T3	11		T27	15		T28	1
auto[1]	auto[0]	interest[1]	1124	1			T3	12		T27	4		T29	15
auto[1]	auto[0]	interest[4]	6645	1			T3	69		T13	2		T27	44
auto[1]	auto[0]	interest[64]	3271	1			T3	47		T13	1		T27	24

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal