Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2758030	1			T1	3171		T2	1		T3	1
all_values[1]	2758030	1			T1	3171		T2	1		T3	1
all_values[2]	2758030	1			T1	3171		T2	1		T3	1
all_values[3]	2758030	1			T1	3171		T2	1		T3	1
all_values[4]	2758030	1			T1	3171		T2	1		T3	1
all_values[5]	2758030	1			T1	3171		T2	1		T3	1
all_values[6]	2758030	1			T1	3171		T2	1		T3	1
all_values[7]	2758030	1			T1	3171		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256025

1

T1

25368

T2

8

T3

8

auto[1]

808215

1

T13

63

T68

62193

T14

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22036067

1

T1

25223

T2

8

T3

8

auto[1]

28173

1

T1

145

T5

212

T6

157

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2659791	1			T1	3105		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	13339	1			T1	66		T5	82		T6	91
all_values[0]	auto[1]	auto[0]	84421	1			T13	4		T68	3		T15	6
all_values[0]	auto[1]	auto[1]	479	1			T13	1		T15	7		T16	6
all_values[1]	auto[0]	auto[0]	2655762	1			T1	3112		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	8490	1			T1	59		T5	76		T6	59
all_values[1]	auto[1]	auto[0]	93384	1			T13	4		T68	2		T14	3
all_values[1]	auto[1]	auto[1]	394	1			T13	2		T68	1		T14	1
all_values[2]	auto[0]	auto[0]	2643513	1			T1	3151		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3232	1			T1	20		T5	54		T6	7
all_values[2]	auto[1]	auto[0]	111030	1			T13	8		T68	2		T14	1
all_values[2]	auto[1]	auto[1]	255	1			T13	2		T68	1		T14	3
all_values[3]	auto[0]	auto[0]	2665700	1			T1	3171		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	217	1			T13	2		T68	3		T15	3
all_values[3]	auto[1]	auto[0]	91931	1			T13	3		T14	2		T15	5
all_values[3]	auto[1]	auto[1]	182	1			T13	6		T68	1		T14	2
all_values[4]	auto[0]	auto[0]	2644703	1			T1	3171		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	191	1			T68	2		T15	5		T16	7
all_values[4]	auto[1]	auto[0]	112941	1			T13	10		T68	1		T14	1
all_values[4]	auto[1]	auto[1]	195	1			T13	2		T15	5		T16	1
all_values[5]	auto[0]	auto[0]	2617822	1			T1	3171		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	172	1			T13	3		T14	1		T15	2
all_values[5]	auto[1]	auto[0]	139848	1			T13	8		T68	20727		T14	1
all_values[5]	auto[1]	auto[1]	188	1			T68	1		T14	1		T15	6
all_values[6]	auto[0]	auto[0]	2649248	1			T1	3171		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	183	1			T13	2		T68	2		T14	2
all_values[6]	auto[1]	auto[0]	108360	1			T13	3		T68	20726		T15	6
all_values[6]	auto[1]	auto[1]	239	1			T13	4		T68	1		T14	1
all_values[7]	auto[0]	auto[0]	2693441	1			T1	3171		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	221	1			T13	5		T15	1		T16	1
all_values[7]	auto[1]	auto[0]	64172	1			T13	2		T68	20725		T14	1
all_values[7]	auto[1]	auto[1]	196	1			T13	4		T68	2		T15	1