Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	32237	1			T1	36		T3	18		T4	4
auto[SpiFlashAddrCfg]	6514	1			T1	13		T4	2		T5	46
auto[SpiFlashAddr3b]	7776	1			T1	9		T4	2		T5	35
auto[SpiFlashAddr4b]	6620	1			T1	4		T4	2		T5	59

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29980

1

T1

35

T3

18

T4

10

auto[1]

23167

1

T1

27

T5

311

T6

178

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27997

1

T1

23

T3

18

T4

6

auto[1]

25150

1

T1

39

T4

4

T5

275

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	36307	1			T1	44		T3	18		T4	4
values[1]	944	1			T5	3		T6	1		T33	2
values[2]	1219	1			T1	1		T5	8		T6	11
values[3]	1222	1			T1	2		T4	2		T5	7
values[4]	1267	1			T5	14		T6	11		T33	6
values[5]	1281	1			T5	3		T6	6		T8	2
values[6]	1252	1			T1	1		T4	2		T5	7
values[7]	1198	1			T1	3		T5	3		T6	2
values[8]	8457	1			T1	11		T4	2		T5	55

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28308

1

T3

18

T4

10

T6

292

auto[1]

24839

1

T1

62

T5

521

T10

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

50387

1

T1

57

T3

18

T4

10

write

2760

1

T1

5

T5

33

T6

15

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16277

1

T1

20

T3

18

T4

6

valids[0x1]

36870

1

T1

42

T4

4

T5

401

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1364	1			T1	1		T5	13		T6	8
internal_process_ops[0x5a]	1374	1			T1	3		T5	7		T6	4
internal_process_ops[0x05]	20468	1			T1	22		T4	2		T5	286
internal_process_ops[0x35]	1391	1			T1	2		T5	9		T6	6
internal_process_ops[0x15]	1343	1			T1	2		T5	11		T6	5
internal_process_ops[0x03]	1021	1			T5	1		T6	4		T8	2
internal_process_ops[0x0b]	959	1			T1	1		T5	2		T6	5
internal_process_ops[0x3b]	889	1			T1	1		T6	5		T10	1
internal_process_ops[0x6b]	993	1			T1	1		T4	2		T5	5
internal_process_ops[0xbb]	929	1			T4	2		T5	3		T6	9
internal_process_ops[0xeb]	929	1			T1	2		T5	5		T6	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51802

1

T1

59

T3

18

T4

10

auto[1]

1345

1

T1

3

T5

22

T6

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51157

1

T1

55

T3

18

T4

10

auto[1]

1990

1

T1

7

T5

18

T6

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9801

1

T3

18

T4

4

T6

63

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6027

1

T6

115

T40

26

T35

13

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1876

1

T4

2

T6

14

T8

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1589

1

T6

16

T40

30

T35

7

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2259

1

T4

2

T6

12

T7

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1868

1

T6

25

T40

30

T35

16

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1872

1

T4

2

T6

17

T40

21

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1643

1

T6

15

T40

17

T35

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

99

1

T6

2

T8

2

T41

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

81

1

T6

2

T35

1

T12

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

65

1

T40

2

T12

2

T44

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

92

1

T40

3

T12

1

T46

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

118

1

T12

2

T44

4

T42

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

57

1

T40

1

T35

1

T12

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

68

1

T44

1

T47

1

T179

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

103

1

T6

1

T40

1

T42

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

94

1

T6

3

T40

3

T44

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

82

1

T40

1

T12

1

T42

5

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

90

1

T6

2

T40

6

T12

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

78

1

T6

4

T40

1

T12

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

112

1

T6

1

T8

4

T40

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

67

1

T40

2

T12

5

T44

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

78

1

T35

1

T42

2

T178

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

89

1

T40

5

T35

4

T45

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8956

1

T1

23

T5

143

T33

49

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6789

1

T1

11

T5

235

T33

11

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1172

1

T1

7

T5

24

T33

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1154

1

T1

3

T5

20

T33

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1496

1

T1

3

T5

12

T33

13

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1475

1

T1

6

T5

14

T33

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1198

1

T5

18

T10

1

T33

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1212

1

T1

4

T5

22

T33

9

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

88

1

T83

1

T180

3

T181

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

81

1

T5

3

T22

1

T23

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

93

1

T1

1

T87

2

T42

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

65

1

T1

1

T87

1

T83

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

71

1

T1

1

T23

1

T182

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

101

1

T1

1

T5

1

T22

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

92

1

T5

1

T33

2

T87

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

113

1

T1

1

T22

1

T23

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

68

1

T5

1

T22

2

T23

6

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

71

1

T33

1

T183

2

T42

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

91

1

T33

2

T23

1

T182

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

104

1

T5

8

T23

3

T42

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

71

1

T5

1

T33

2

T22

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

89

1

T5

7

T87

4

T42

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

117

1

T5

8

T42

3

T83

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

72

1

T5

3

T33

1

T22

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3317	1			T3	18		T6	26		T40	37
auto[0]	values[0]	valids[0x1]	15005	1			T4	4		T6	182		T7	6
auto[0]	values[1]	valids[0x1]	506	1			T6	1		T40	8		T35	3
auto[0]	values[2]	valids[0x0]	457	1			T6	4		T40	2		T35	4
auto[0]	values[2]	valids[0x1]	243	1			T6	7		T40	5		T35	2
auto[0]	values[3]	valids[0x0]	475	1			T4	2		T6	4		T7	2
auto[0]	values[3]	valids[0x1]	275	1			T9	8		T40	4		T35	6
auto[0]	values[4]	valids[0x0]	532	1			T6	8		T40	8		T12	6
auto[0]	values[4]	valids[0x1]	260	1			T6	3		T40	5		T35	2
auto[0]	values[5]	valids[0x0]	535	1			T6	3		T8	2		T40	5
auto[0]	values[5]	valids[0x1]	246	1			T6	3		T40	2		T35	1
auto[0]	values[6]	valids[0x0]	475	1			T4	2		T6	11		T40	3
auto[0]	values[6]	valids[0x1]	287	1			T40	7		T12	3		T44	9
auto[0]	values[7]	valids[0x0]	465	1			T6	1		T8	2		T40	7
auto[0]	values[7]	valids[0x1]	238	1			T6	1		T40	2		T35	2
auto[0]	values[8]	valids[0x0]	3078	1			T4	2		T6	25		T8	2
auto[0]	values[8]	valids[0x1]	1914	1			T6	13		T8	2		T40	31
auto[1]	values[0]	valids[0x0]	3239	1			T1	10		T5	60		T33	29
auto[1]	values[0]	valids[0x1]	14746	1			T1	34		T5	361		T33	48
auto[1]	values[1]	valids[0x1]	438	1			T5	3		T33	2		T22	4
auto[1]	values[2]	valids[0x0]	276	1			T1	1		T5	6		T33	5
auto[1]	values[2]	valids[0x1]	243	1			T5	2		T22	1		T23	5
auto[1]	values[3]	valids[0x0]	261	1			T1	1		T5	7		T22	5
auto[1]	values[3]	valids[0x1]	211	1			T1	1		T33	1		T22	3
auto[1]	values[4]	valids[0x0]	275	1			T5	7		T33	4		T22	1
auto[1]	values[4]	valids[0x1]	200	1			T5	7		T33	2		T22	1
auto[1]	values[5]	valids[0x0]	296	1			T5	1		T22	1		T23	5
auto[1]	values[5]	valids[0x1]	204	1			T5	2		T33	2		T22	2
auto[1]	values[6]	valids[0x0]	267	1			T1	1		T5	4		T22	3
auto[1]	values[6]	valids[0x1]	223	1			T5	3		T33	2		T87	1
auto[1]	values[7]	valids[0x0]	284	1			T1	2		T5	2		T33	4
auto[1]	values[7]	valids[0x1]	211	1			T1	1		T5	1		T33	1
auto[1]	values[8]	valids[0x0]	2045	1			T1	5		T5	33		T10	1
auto[1]	values[8]	valids[0x1]	1420	1			T1	6		T5	22		T33	4