Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3119773

1

T1

3329

T3

469

T4

7

auto[1]

19128

1

T1

22

T5

281

T6

132

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068047

1

T1

28

T3

469

T4

1

auto[1]

2070854

1

T1

3323

T4

6

T5

11270

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	551034	1			T1	22		T3	7		T4	7
auto[524288:1048575]	347984	1			T1	1		T3	410		T5	794
auto[1048576:1572863]	421153	1			T1	15		T5	1651		T6	5040
auto[1572864:2097151]	406146	1			T1	3		T3	5		T5	646
auto[2097152:2621439]	278438	1			T3	3		T5	3		T9	3
auto[2621440:3145727]	373202	1			T1	150		T3	20		T5	2342
auto[3145728:3670015]	381021	1			T1	2903		T3	10		T5	853
auto[3670016:4194303]	379923	1			T1	257		T3	14		T5	1806

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2090674

1

T1

3351

T3

23

T4

7

auto[1]

1048227

1

T3

446

T5

6

T6

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2731079

1

T1

3351

T3

469

T4

7

auto[1]

407822

1

T5

4545

T33

3199

T40

3755

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	189304	1			T1	5		T3	7		T4	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	302181	1			T1	15		T4	6		T5	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	130966	1			T1	1		T3	410		T5	6
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	172223	1			T5	514		T40	2813		T35	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	131035	1			T1	5		T5	11		T6	14
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	232232	1			T1	3		T5	1056		T6	5017
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	127432	1			T1	1		T3	5		T5	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	221190	1			T1	1		T5	640		T40	6372
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	99387	1			T3	3		T5	3		T9	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	133436	1			T40	2		T12	1501		T22	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	113590	1			T1	8		T3	20		T5	9
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	208164	1			T1	130		T5	2063		T6	3487
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	121784	1			T3	10		T5	7		T7	966
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	200240	1			T1	2903		T5	515		T6	256
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	140321	1			T1	1		T3	14		T5	11
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	192879	1			T1	256		T5	1691		T6	257
auto[0]	auto[1]	auto[0:524287]	auto[0]	264	1			T5	3		T33	2		T40	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	56109	1			T5	3244		T33	1868		T40	1024
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	310	1			T5	1		T33	4		T40	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	42158	1			T5	257		T33	46		T40	209
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	3347	1			T5	4		T40	1		T35	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	52039	1			T5	513		T40	1		T35	472
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	557	1			T5	3		T33	10		T40	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	54606	1			T33	934		T40	2481		T35	8
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1617	1			T40	2		T12	3		T23	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	41915	1			T40	1		T12	1		T23	261
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	4427	1			T5	1		T40	1		T23	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	44838	1			T5	256		T33	256		T23	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	273	1			T5	3		T12	1		T44	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	56264	1			T5	256		T44	2839		T45	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1441	1			T33	3		T40	3		T22	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	43244	1			T33	62		T40	1		T23	1507
auto[1]	auto[0]	auto[0:524287]	auto[0]	274	1			T1	1		T5	2		T6	7
auto[1]	auto[0]	auto[0:524287]	auto[1]	2405	1			T1	1		T5	7		T6	104
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	201	1			T5	2		T40	1		T22	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1711	1			T5	14		T40	14		T23	13
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	204	1			T1	3		T5	2		T6	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1712	1			T1	4		T5	61		T6	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	193	1			T1	1		T23	1		T44	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1490	1			T44	3		T42	1		T47	40
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	154	1			T40	2		T22	3		T44	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1311	1			T40	18		T22	3		T44	31
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	187	1			T1	2		T5	2		T6	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1305	1			T1	10		T5	11		T6	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	204	1			T5	3		T33	1		T23	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1808	1			T5	69		T33	2		T23	8
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	182	1			T5	6		T6	1		T12	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1374	1			T5	98		T6	5		T12	11
auto[1]	auto[1]	auto[0:524287]	auto[0]	39	1			T33	1		T23	1		T42	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	458	1			T33	1		T42	1		T180	12
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	38	1			T33	3		T23	1		T47	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	377	1			T23	4		T47	7		T228	127
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	53	1			T5	1		T40	1		T180	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	531	1			T5	3		T40	8		T180	36
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	60	1			T33	4		T244	1		T68	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	618	1			T33	1		T244	61		T68	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	47	1			T40	1		T12	1		T23	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	571	1			T40	10		T12	2		T23	17
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	64	1			T44	1		T42	1		T182	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	627	1			T44	2		T42	8		T182	11
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	42	1			T44	1		T45	1		T183	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	406	1			T44	9		T45	23		T183	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	50	1			T33	1		T40	1		T23	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	432	1			T33	3		T40	3		T23	7

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1678661	1			T1	3329		T3	23		T4	7
auto[0]	auto[0]	auto[1]	1037703	1			T3	446		T5	5		T6	2
auto[0]	auto[1]	auto[0]	393233	1			T5	4541		T33	3185		T40	3731
auto[0]	auto[1]	auto[1]	10176	1			T44	1		T45	1		T89	17
auto[1]	auto[0]	auto[0]	14456	1			T1	22		T5	276		T6	132
auto[1]	auto[0]	auto[1]	259	1			T5	1		T40	8		T22	1
auto[1]	auto[1]	auto[0]	4324	1			T5	4		T33	12		T40	22
auto[1]	auto[1]	auto[1]	89	1			T33	2		T40	2		T44	2