Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16518

1

T3

18

T4

10

T6

114

auto[1]

11790

1

T6

178

T40

121

T35

46

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4107	1			T40	42		T113	16		T12	133
values[1]	3513	1			T6	171		T40	104		T12	32
values[2]	3754	1			T6	45		T8	18		T40	110
values[3]	3419	1			T9	10		T40	40		T12	20
values[4]	3909	1			T3	18		T40	60		T41	18
values[5]	2978	1			T6	30		T7	8		T40	41
values[6]	3457	1			T4	10		T6	46		T40	40
values[7]	3171	1			T12	43		T45	73		T42	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3044	1			T40	20		T12	20		T44	60
values[1]	3529	1			T6	26		T40	104		T35	42
values[2]	3546	1			T3	18		T6	196		T9	10
values[3]	3920	1			T7	8		T40	101		T41	18
values[4]	3232	1			T8	18		T40	110		T35	20
values[5]	3777	1			T4	10		T6	50		T40	20
values[6]	3050	1			T6	20		T40	40		T44	40
values[7]	4210	1			T40	42		T35	20		T12	43

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	329	1			T12	11		T47	28		T178	12
auto[0]	values[0]	values[1]	295	1			T12	27		T201	52		T215	13
auto[0]	values[0]	values[2]	211	1			T113	16		T12	8		T48	8
auto[0]	values[0]	values[3]	394	1			T12	18		T44	78		T208	14
auto[0]	values[0]	values[4]	389	1			T20	11		T57	11		T230	25
auto[0]	values[0]	values[5]	296	1			T12	14		T177	14		T17	10
auto[0]	values[0]	values[6]	355	1			T225	10		T234	11		T54	8
auto[0]	values[0]	values[7]	260	1			T40	29		T42	14		T14	34
auto[0]	values[1]	values[0]	256	1			T172	16		T218	12		T68	7
auto[0]	values[1]	values[1]	219	1			T40	35		T45	20		T198	67
auto[0]	values[1]	values[2]	172	1			T6	39		T245	4		T92	35
auto[0]	values[1]	values[3]	287	1			T40	51		T30	6		T42	27
auto[0]	values[1]	values[4]	195	1			T222	36		T231	14		T246	13
auto[0]	values[1]	values[5]	288	1			T12	22		T44	12		T47	10
auto[0]	values[1]	values[6]	254	1			T6	11		T45	15		T48	15
auto[0]	values[1]	values[7]	292	1			T178	25		T215	14		T207	8
auto[0]	values[2]	values[0]	242	1			T40	20		T44	13		T201	6
auto[0]	values[2]	values[1]	403	1			T158	16		T42	26		T48	7
auto[0]	values[2]	values[2]	261	1			T6	34		T42	19		T48	14
auto[0]	values[2]	values[3]	259	1			T57	17		T247	10		T236	22
auto[0]	values[2]	values[4]	447	1			T8	18		T40	77		T35	12
auto[0]	values[2]	values[5]	438	1			T45	10		T48	13		T197	8
auto[0]	values[2]	values[6]	182	1			T47	12		T178	10		T208	35
auto[0]	values[2]	values[7]	127	1			T42	14		T232	14		T248	2
auto[0]	values[3]	values[0]	304	1			T44	11		T208	9		T233	63
auto[0]	values[3]	values[1]	296	1			T40	7		T48	18		T68	12
auto[0]	values[3]	values[2]	210	1			T9	10		T198	11		T249	10
auto[0]	values[3]	values[3]	246	1			T178	9		T225	13		T234	22
auto[0]	values[3]	values[4]	272	1			T250	4		T251	4		T20	19
auto[0]	values[3]	values[5]	174	1			T40	9		T12	12		T252	6
auto[0]	values[3]	values[6]	205	1			T44	9		T253	2		T254	16
auto[0]	values[3]	values[7]	260	1			T178	43		T255	143		T217	14
auto[0]	values[4]	values[0]	331	1			T42	5		T179	11		T14	15
auto[0]	values[4]	values[1]	220	1			T44	16		T45	9		T17	14
auto[0]	values[4]	values[2]	178	1			T3	18		T225	9		T14	8
auto[0]	values[4]	values[3]	245	1			T40	8		T41	18		T201	11
auto[0]	values[4]	values[4]	269	1			T68	23		T201	15		T20	32
auto[0]	values[4]	values[5]	209	1			T178	11		T256	14		T208	11
auto[0]	values[4]	values[6]	207	1			T40	30		T44	9		T20	15
auto[0]	values[4]	values[7]	713	1			T48	9		T178	142		T208	8
auto[0]	values[5]	values[0]	204	1			T89	20		T48	10		T15	17
auto[0]	values[5]	values[1]	275	1			T40	32		T44	12		T42	17
auto[0]	values[5]	values[2]	333	1			T209	6		T42	8		T206	24
auto[0]	values[5]	values[3]	131	1			T7	8		T68	15		T14	18
auto[0]	values[5]	values[4]	143	1			T44	7		T14	15		T195	13
auto[0]	values[5]	values[5]	205	1			T6	8		T227	14		T247	29
auto[0]	values[5]	values[6]	183	1			T42	11		T208	8		T224	9
auto[0]	values[5]	values[7]	242	1			T12	8		T47	100		T207	10
auto[0]	values[6]	values[0]	157	1			T215	18		T257	16		T246	21
auto[0]	values[6]	values[1]	236	1			T6	11		T35	25		T238	16
auto[0]	values[6]	values[2]	307	1			T12	24		T44	13		T258	2
auto[0]	values[6]	values[3]	389	1			T40	10		T192	2		T47	93
auto[0]	values[6]	values[4]	160	1			T40	8		T223	20		T208	9
auto[0]	values[6]	values[5]	224	1			T4	10		T6	11		T35	9
auto[0]	values[6]	values[6]	292	1			T234	13		T20	17		T53	6
auto[0]	values[6]	values[7]	180	1			T35	10		T42	20		T178	11
auto[0]	values[7]	values[0]	101	1			T133	2		T247	12		T207	18
auto[0]	values[7]	values[1]	258	1			T12	14		T48	15		T178	13
auto[0]	values[7]	values[2]	236	1			T143	54		T259	8		T260	8
auto[0]	values[7]	values[3]	92	1			T45	11		T48	9		T178	9
auto[0]	values[7]	values[4]	102	1			T261	10		T57	10		T166	15
auto[0]	values[7]	values[5]	258	1			T68	14		T220	5		T195	43
auto[0]	values[7]	values[6]	142	1			T42	15		T47	22		T208	10
auto[0]	values[7]	values[7]	478	1			T12	9		T45	10		T68	11
auto[1]	values[0]	values[0]	227	1			T12	9		T47	8		T178	8
auto[1]	values[0]	values[1]	264	1			T12	26		T201	6		T215	7
auto[1]	values[0]	values[2]	167	1			T12	12		T48	12		T208	55
auto[1]	values[0]	values[3]	327	1			T12	2		T44	24		T208	6
auto[1]	values[0]	values[4]	206	1			T20	13		T57	9		T230	22
auto[1]	values[0]	values[5]	110	1			T12	6		T17	10		T215	6
auto[1]	values[0]	values[6]	156	1			T225	10		T234	12		T207	10
auto[1]	values[0]	values[7]	121	1			T40	13		T42	7		T14	10
auto[1]	values[1]	values[0]	62	1			T218	13		T68	19		T262	9
auto[1]	values[1]	values[1]	127	1			T40	8		T45	20		T198	21
auto[1]	values[1]	values[2]	233	1			T6	112		T20	8		T57	46
auto[1]	values[1]	values[3]	195	1			T40	10		T42	14		T47	36
auto[1]	values[1]	values[4]	235	1			T222	4		T231	6		T263	4
auto[1]	values[1]	values[5]	175	1			T12	10		T44	8		T47	17
auto[1]	values[1]	values[6]	230	1			T6	9		T45	5		T48	5
auto[1]	values[1]	values[7]	293	1			T178	147		T215	6		T207	12
auto[1]	values[2]	values[0]	164	1			T44	7		T201	20		T195	11
auto[1]	values[2]	values[1]	175	1			T42	26		T48	13		T179	11
auto[1]	values[2]	values[2]	237	1			T6	11		T42	4		T48	10
auto[1]	values[2]	values[3]	162	1			T57	3		T247	12		T212	6
auto[1]	values[2]	values[4]	168	1			T40	13		T35	8		T208	7
auto[1]	values[2]	values[5]	284	1			T45	10		T48	12		T234	6
auto[1]	values[2]	values[6]	83	1			T47	8		T178	10		T208	7
auto[1]	values[2]	values[7]	122	1			T42	6		T232	6		T262	19
auto[1]	values[3]	values[0]	135	1			T44	29		T208	11		T234	9
auto[1]	values[3]	values[1]	148	1			T40	13		T48	3		T68	8
auto[1]	values[3]	values[2]	137	1			T198	9		T249	12		T246	13
auto[1]	values[3]	values[3]	337	1			T178	34		T225	7		T234	111
auto[1]	values[3]	values[4]	219	1			T20	9		T194	12		T264	9
auto[1]	values[3]	values[5]	220	1			T40	11		T12	8		T27	6
auto[1]	values[3]	values[6]	94	1			T44	11		T265	9		T266	13
auto[1]	values[3]	values[7]	162	1			T178	17		T255	5		T267	16
auto[1]	values[4]	values[0]	211	1			T42	15		T179	10		T14	5
auto[1]	values[4]	values[1]	77	1			T44	4		T45	11		T17	6
auto[1]	values[4]	values[2]	143	1			T225	11		T14	12		T249	9
auto[1]	values[4]	values[3]	356	1			T40	12		T46	26		T201	64
auto[1]	values[4]	values[4]	113	1			T68	23		T201	5		T20	13
auto[1]	values[4]	values[5]	224	1			T178	9		T208	79		T68	10
auto[1]	values[4]	values[6]	123	1			T40	10		T44	11		T20	5
auto[1]	values[4]	values[7]	290	1			T48	11		T178	9		T208	39
auto[1]	values[5]	values[0]	109	1			T48	10		T15	7		T17	10
auto[1]	values[5]	values[1]	215	1			T40	9		T44	12		T42	6
auto[1]	values[5]	values[2]	147	1			T42	23		T247	15		T166	20
auto[1]	values[5]	values[3]	117	1			T68	5		T14	8		T20	8
auto[1]	values[5]	values[4]	82	1			T44	13		T14	8		T195	7
auto[1]	values[5]	values[5]	247	1			T6	22		T247	19		T268	18
auto[1]	values[5]	values[6]	121	1			T42	11		T208	12		T224	12
auto[1]	values[5]	values[7]	224	1			T12	12		T47	22		T226	14
auto[1]	values[6]	values[0]	110	1			T237	14		T215	4		T246	4
auto[1]	values[6]	values[1]	98	1			T6	15		T35	17		T44	7
auto[1]	values[6]	values[2]	486	1			T12	16		T44	12		T68	7
auto[1]	values[6]	values[3]	208	1			T40	10		T47	14		T208	11
auto[1]	values[6]	values[4]	76	1			T40	12		T208	11		T234	12
auto[1]	values[6]	values[5]	171	1			T6	9		T35	11		T47	4
auto[1]	values[6]	values[6]	202	1			T234	10		T20	3		T57	8
auto[1]	values[6]	values[7]	161	1			T35	10		T42	25		T178	9
auto[1]	values[7]	values[0]	102	1			T247	8		T207	5		T269	14
auto[1]	values[7]	values[1]	223	1			T12	6		T48	5		T178	7
auto[1]	values[7]	values[2]	88	1			T143	9		T270	14		T271	8
auto[1]	values[7]	values[3]	175	1			T45	33		T48	11		T178	59
auto[1]	values[7]	values[4]	156	1			T57	10		T166	5		T272	18
auto[1]	values[7]	values[5]	254	1			T68	7		T220	15		T195	87
auto[1]	values[7]	values[6]	221	1			T42	5		T47	10		T273	4
auto[1]	values[7]	values[7]	285	1			T12	14		T45	19		T68	10