Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2758030	1			T1	3171		T2	1		T3	1
all_pins[1]	2758030	1			T1	3171		T2	1		T3	1
all_pins[2]	2758030	1			T1	3171		T2	1		T3	1
all_pins[3]	2758030	1			T1	3171		T2	1		T3	1
all_pins[4]	2758030	1			T1	3171		T2	1		T3	1
all_pins[5]	2758030	1			T1	3171		T2	1		T3	1
all_pins[6]	2758030	1			T1	3171		T2	1		T3	1
all_pins[7]	2758030	1			T1	3171		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21951748	1			T1	25368		T2	8		T3	8
values[0x1]	112492	1			T13	21		T68	21373		T14	8
transitions[0x0=>0x1]	110305	1			T13	14		T68	20709		T14	6
transitions[0x1=>0x0]	110317	1			T13	14		T68	20709		T14	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2757506	1			T1	3171		T2	1		T3	1
all_pins[0]	values[0x1]	524	1			T13	1		T15	7		T16	6
all_pins[0]	transitions[0x0=>0x1]	324	1			T13	1		T15	2		T16	4
all_pins[0]	transitions[0x1=>0x0]	216	1			T13	2		T68	1		T14	1
all_pins[1]	values[0x0]	2757614	1			T1	3171		T2	1		T3	1
all_pins[1]	values[0x1]	416	1			T13	2		T68	1		T14	1
all_pins[1]	transitions[0x0=>0x1]	304	1			T13	2		T68	1		T14	1
all_pins[1]	transitions[0x1=>0x0]	157	1			T13	2		T68	1		T14	3
all_pins[2]	values[0x0]	2757761	1			T1	3171		T2	1		T3	1
all_pins[2]	values[0x1]	269	1			T13	2		T68	1		T14	3
all_pins[2]	transitions[0x0=>0x1]	227	1			T68	1		T14	1		T15	4
all_pins[2]	transitions[0x1=>0x0]	140	1			T13	4		T68	1		T15	1
all_pins[3]	values[0x0]	2757848	1			T1	3171		T2	1		T3	1
all_pins[3]	values[0x1]	182	1			T13	6		T68	1		T14	2
all_pins[3]	transitions[0x0=>0x1]	144	1			T13	4		T68	1		T14	2
all_pins[3]	transitions[0x1=>0x0]	157	1			T15	5		T16	1		T17	4
all_pins[4]	values[0x0]	2757835	1			T1	3171		T2	1		T3	1
all_pins[4]	values[0x1]	195	1			T13	2		T15	5		T16	1
all_pins[4]	transitions[0x0=>0x1]	156	1			T13	2		T15	3		T16	1
all_pins[4]	transitions[0x1=>0x0]	2459	1			T68	668		T14	1		T15	4
all_pins[5]	values[0x0]	2755532	1			T1	3171		T2	1		T3	1
all_pins[5]	values[0x1]	2498	1			T68	668		T14	1		T15	6
all_pins[5]	transitions[0x0=>0x1]	863	1			T68	4		T14	1		T15	4
all_pins[5]	transitions[0x1=>0x0]	106577	1			T13	4		T68	20036		T14	1
all_pins[6]	values[0x0]	2649818	1			T1	3171		T2	1		T3	1
all_pins[6]	values[0x1]	108212	1			T13	4		T68	20700		T14	1
all_pins[6]	transitions[0x0=>0x1]	108146	1			T13	2		T68	20700		T14	1
all_pins[6]	transitions[0x1=>0x0]	130	1			T13	2		T68	2		T15	1
all_pins[7]	values[0x0]	2757834	1			T1	3171		T2	1		T3	1
all_pins[7]	values[0x1]	196	1			T13	4		T68	2		T15	1
all_pins[7]	transitions[0x0=>0x1]	141	1			T13	3		T68	2		T15	1
all_pins[7]	transitions[0x1=>0x0]	481	1			T15	7		T16	4		T17	1