Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	433	1			T40	5		T35	1		T158	8
auto[ReadAddrCrossIntoMailbox]	257	1			T6	3		T40	3		T35	4
auto[ReadAddrCrossOutOfMailbox]	318	1			T6	4		T40	6		T35	5
auto[ReadAddrCrossAllMailbox]	197	1			T40	1		T35	2		T44	2
auto[ReadAddrOutsideMailbox]	3252	1			T4	4		T6	26		T7	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2260

1

T4

2

T6

19

T7

2

auto[1]

2197

1

T4

2

T6

14

T7

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	791	1			T6	4		T8	2		T9	8
read_ops[0x0b]	748	1			T6	5		T7	2		T40	11
read_ops[0x3b]	679	1			T6	5		T40	10		T35	4
read_ops[0x6b]	768	1			T4	2		T6	7		T40	9
read_ops[0xbb]	727	1			T4	2		T6	9		T7	2
read_ops[0xeb]	744	1			T6	3		T40	3		T35	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T40	2		T113	3		T12	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T40	1		T113	3		T12	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T178	1		T68	1		T194	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T40	1		T12	1		T48	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T47	1		T178	1		T208	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T40	1		T47	2		T48	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T35	1		T42	1		T48	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T40	1		T44	1		T47	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T6	3		T8	1		T9	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	297	1			T6	1		T8	1		T9	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T158	3		T45	1		T218	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T40	1		T158	3		T12	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T6	1		T45	1		T220	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T12	3		T48	2		T194	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T40	2		T35	1		T12	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T201	1		T194	1		T274	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T35	1		T45	1		T42	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T178	1		T14	2		T201	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T6	3		T7	1		T40	7
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T6	1		T7	1		T40	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T47	1		T68	1		T197	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T40	1		T48	1		T179	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T45	1		T47	1		T15	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T44	1		T45	1		T215	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T12	3		T42	1		T225	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T6	1		T40	3		T35	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T42	2		T48	1		T15	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T208	2		T68	1		T234	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	257	1			T6	4		T40	4		T35	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	233	1			T40	2		T35	1		T12	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T35	1		T12	1		T178	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	48	1			T12	1		T44	2		T45	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T6	1		T35	1		T14	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T44	1		T47	1		T68	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T6	1		T35	1		T12	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T48	1		T218	1		T57	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T42	1		T15	1		T234	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T44	1		T234	1		T215	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	274	1			T4	1		T6	3		T40	6
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	267	1			T4	1		T6	2		T40	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T158	1		T113	2		T44	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T158	1		T113	2		T12	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T40	1		T44	2		T208	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T6	1		T35	1		T48	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T12	1		T44	1		T201	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	39	1			T6	1		T35	2		T45	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T218	1		T68	1		T261	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T42	1		T68	1		T261	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	272	1			T4	1		T7	1		T8	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	255	1			T4	1		T6	7		T7	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T68	1		T197	1		T20	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T47	1		T208	1		T197	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T35	2		T45	2		T179	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T40	1		T48	1		T215	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T6	1		T179	1		T218	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T44	2		T48	2		T57	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T48	1		T201	1		T249	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T14	1		T17	1		T215	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	254	1			T6	2		T40	1		T35	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T40	1		T35	1		T41	2