Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2948	1			T6	56		T8	18		T12	20
values[1]	3744	1			T4	10		T40	20		T35	20
values[2]	3635	1			T6	45		T7	8		T40	81
values[3]	3498	1			T6	20		T9	10		T40	81
values[4]	3667	1			T3	18		T6	125		T40	42
values[5]	4035	1			T40	40		T12	32		T44	20
values[6]	2923	1			T6	26		T40	173		T12	20
values[7]	3858	1			T6	20		T158	16		T12	43

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4098	1			T6	30		T8	18		T40	112
values[1]	3164	1			T3	18		T6	40		T7	8
values[2]	3099	1			T4	10		T40	40		T12	20
values[3]	3463	1			T6	26		T35	42		T12	60
values[4]	2999	1			T6	20		T40	41		T35	20
values[5]	4015	1			T40	103		T41	18		T158	16
values[6]	4212	1			T6	150		T113	16		T12	96
values[7]	3258	1			T6	26		T9	10		T40	121

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27659

1

T3

18

T4

10

T6

285

auto[1]

649

1

T6

7

T40

14

T35

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	359	1			T6	30		T8	18		T44	20
auto[0]	values[0]	values[1]	308	1			T42	22		T14	22		T201	25
auto[0]	values[0]	values[2]	512	1			T42	20		T48	24		T177	14
auto[0]	values[0]	values[3]	474	1			T6	26		T12	19		T42	45
auto[0]	values[0]	values[4]	415	1			T44	23		T45	19		T201	77
auto[0]	values[0]	values[5]	353	1			T48	20		T275	2		T234	131
auto[0]	values[0]	values[6]	225	1			T27	6		T224	20		T276	12
auto[0]	values[0]	values[7]	224	1			T44	20		T45	20		T253	2
auto[0]	values[1]	values[0]	454	1			T45	44		T258	2		T68	17
auto[0]	values[1]	values[1]	290	1			T40	20		T42	20		T234	56
auto[0]	values[1]	values[2]	514	1			T4	10		T47	44		T208	47
auto[0]	values[1]	values[3]	323	1			T47	20		T178	40		T225	19
auto[0]	values[1]	values[4]	371	1			T178	68		T68	45		T201	72
auto[0]	values[1]	values[5]	585	1			T41	18		T45	18		T178	41
auto[0]	values[1]	values[6]	536	1			T225	20		T14	46		T277	4
auto[0]	values[1]	values[7]	597	1			T35	19		T47	186		T48	18
auto[0]	values[2]	values[0]	384	1			T47	31		T256	14		T57	21
auto[0]	values[2]	values[1]	471	1			T7	8		T68	24		T137	4
auto[0]	values[2]	values[2]	302	1			T237	14		T42	27		T249	22
auto[0]	values[2]	values[3]	528	1			T35	17		T12	19		T46	24
auto[0]	values[2]	values[4]	341	1			T12	18		T48	20		T234	20
auto[0]	values[2]	values[5]	490	1			T40	19		T178	49		T15	23
auto[0]	values[2]	values[6]	520	1			T6	43		T218	20		T208	66
auto[0]	values[2]	values[7]	507	1			T40	58		T229	26		T57	20
auto[0]	values[3]	values[0]	471	1			T172	16		T273	4		T208	16
auto[0]	values[3]	values[1]	443	1			T30	6		T42	24		T48	18
auto[0]	values[3]	values[2]	337	1			T40	20		T12	18		T17	77
auto[0]	values[3]	values[3]	280	1			T35	20		T247	22		T246	20
auto[0]	values[3]	values[4]	351	1			T6	19		T40	38		T192	2
auto[0]	values[3]	values[5]	835	1			T238	16		T47	18		T201	28
auto[0]	values[3]	values[6]	363	1			T12	49		T209	6		T48	20
auto[0]	values[3]	values[7]	329	1			T9	10		T40	20		T35	20
auto[0]	values[4]	values[0]	519	1			T40	21		T44	20		T48	22
auto[0]	values[4]	values[1]	653	1			T3	18		T6	20		T42	24
auto[0]	values[4]	values[2]	182	1			T68	20		T246	26		T169	18
auto[0]	values[4]	values[3]	552	1			T12	20		T44	45		T252	6
auto[0]	values[4]	values[4]	294	1			T35	20		T44	20		T42	31
auto[0]	values[4]	values[5]	455	1			T40	20		T179	21		T220	20
auto[0]	values[4]	values[6]	423	1			T6	102		T113	16		T42	21
auto[0]	values[4]	values[7]	506	1			T208	20		T234	20		T247	25
auto[0]	values[5]	values[0]	480	1			T15	20		T17	89		T234	76
auto[0]	values[5]	values[1]	338	1			T197	8		T20	45		T278	14
auto[0]	values[5]	values[2]	484	1			T40	20		T178	116		T179	21
auto[0]	values[5]	values[3]	469	1			T227	14		T206	24		T20	22
auto[0]	values[5]	values[4]	448	1			T12	30		T208	40		T134	16
auto[0]	values[5]	values[5]	487	1			T40	20		T44	20		T45	20
auto[0]	values[5]	values[6]	810	1			T208	61		T233	63		T261	10
auto[0]	values[5]	values[7]	440	1			T47	41		T225	20		T14	44
auto[0]	values[6]	values[0]	500	1			T40	89		T178	19		T208	20
auto[0]	values[6]	values[1]	179	1			T14	20		T191	8		T143	20
auto[0]	values[6]	values[2]	173	1			T45	20		T47	35		T90	18
auto[0]	values[6]	values[3]	352	1			T44	40		T89	20		T214	8
auto[0]	values[6]	values[4]	349	1			T44	20		T42	20		T208	19
auto[0]	values[6]	values[5]	302	1			T40	41		T42	20		T254	16
auto[0]	values[6]	values[6]	703	1			T48	19		T178	150		T220	20
auto[0]	values[6]	values[7]	298	1			T6	25		T40	37		T12	19
auto[0]	values[7]	values[0]	855	1			T44	81		T178	20		T279	16
auto[0]	values[7]	values[1]	406	1			T6	20		T42	20		T179	19
auto[0]	values[7]	values[2]	530	1			T44	22		T178	20		T68	20
auto[0]	values[7]	values[3]	423	1			T178	20		T193	66		T201	20
auto[0]	values[7]	values[4]	345	1			T48	23		T218	23		T14	22
auto[0]	values[7]	values[5]	409	1			T158	16		T44	20		T17	20
auto[0]	values[7]	values[6]	528	1			T12	42		T42	21		T48	20
auto[0]	values[7]	values[7]	275	1			T249	22		T280	6		T262	20
auto[1]	values[0]	values[0]	7	1			T44	1		T230	1		T281	4
auto[1]	values[0]	values[1]	4	1			T42	1		T14	1		T201	1
auto[1]	values[0]	values[2]	12	1			T42	1		T48	1		T255	3
auto[1]	values[0]	values[3]	10	1			T12	1		T42	1		T282	2
auto[1]	values[0]	values[4]	17	1			T44	1		T45	1		T201	1
auto[1]	values[0]	values[5]	8	1			T234	2		T283	3		T284	3
auto[1]	values[0]	values[6]	7	1			T224	1		T166	1		T285	2
auto[1]	values[0]	values[7]	13	1			T246	2		T286	4		T287	2
auto[1]	values[1]	values[0]	8	1			T68	3		T288	1		T205	2
auto[1]	values[1]	values[1]	2	1			T234	1		T198	1		-	-
auto[1]	values[1]	values[2]	9	1			T194	2		T285	2		T143	1
auto[1]	values[1]	values[3]	8	1			T225	1		T270	5		T289	2
auto[1]	values[1]	values[4]	8	1			T68	3		T201	1		T20	2
auto[1]	values[1]	values[5]	11	1			T45	2		T178	2		T290	3
auto[1]	values[1]	values[6]	11	1			T14	2		T57	1		T232	1
auto[1]	values[1]	values[7]	17	1			T35	1		T47	2		T48	2
auto[1]	values[2]	values[0]	10	1			T47	1		T291	1		T292	2
auto[1]	values[2]	values[1]	9	1			T68	1		T282	1		T293	2
auto[1]	values[2]	values[2]	11	1			T42	1		T166	1		T232	2
auto[1]	values[2]	values[3]	12	1			T35	5		T12	1		T46	2
auto[1]	values[2]	values[4]	8	1			T12	2		T20	2		T270	4
auto[1]	values[2]	values[5]	17	1			T40	1		T178	6		T15	1
auto[1]	values[2]	values[6]	15	1			T6	2		T68	3		T230	1
auto[1]	values[2]	values[7]	10	1			T40	3		T166	1		T262	2
auto[1]	values[3]	values[0]	17	1			T208	4		T14	1		T166	3
auto[1]	values[3]	values[1]	14	1			T48	2		T57	1		T195	5
auto[1]	values[3]	values[2]	11	1			T12	2		T17	1		T20	1
auto[1]	values[3]	values[3]	3	1			T246	2		T210	1		-	-
auto[1]	values[3]	values[4]	13	1			T6	1		T40	3		T212	2
auto[1]	values[3]	values[5]	17	1			T47	2		T201	2		T194	1
auto[1]	values[3]	values[6]	12	1			T12	4		T234	1		T265	2
auto[1]	values[3]	values[7]	2	1			T246	1		T292	1		-	-
auto[1]	values[4]	values[0]	6	1			T40	1		T234	1		T264	1
auto[1]	values[4]	values[1]	23	1			T42	3		T20	1		T194	3
auto[1]	values[4]	values[2]	7	1			T246	2		T169	2		T52	2
auto[1]	values[4]	values[3]	8	1			T195	1		T247	1		T166	1
auto[1]	values[4]	values[4]	6	1			T201	2		T52	1		T294	3
auto[1]	values[4]	values[5]	9	1			T179	1		T220	1		T194	1
auto[1]	values[4]	values[6]	15	1			T6	3		T42	1		T166	1
auto[1]	values[4]	values[7]	9	1			T231	1		T285	1		T290	1
auto[1]	values[5]	values[0]	2	1			T15	1		T287	1		-	-
auto[1]	values[5]	values[1]	6	1			T20	3		T285	2		T289	1
auto[1]	values[5]	values[2]	2	1			T178	1		T143	1		-	-
auto[1]	values[5]	values[3]	12	1			T20	2		T246	3		T295	2
auto[1]	values[5]	values[4]	8	1			T12	2		T265	1		T270	2
auto[1]	values[5]	values[5]	19	1			T208	2		T68	1		T207	1
auto[1]	values[5]	values[6]	21	1			T208	1		T272	2		T231	2
auto[1]	values[5]	values[7]	9	1			T201	3		T290	1		T213	1
auto[1]	values[6]	values[0]	5	1			T40	1		T178	1		T52	2
auto[1]	values[6]	values[1]	7	1			T143	2		T205	1		T296	2
auto[1]	values[6]	values[2]	3	1			T47	1		T198	1		T270	1
auto[1]	values[6]	values[3]	8	1			T271	1		T297	4		T298	3
auto[1]	values[6]	values[4]	14	1			T208	1		T207	1		T230	3
auto[1]	values[6]	values[5]	8	1			T40	2		T264	1		T299	4
auto[1]	values[6]	values[6]	10	1			T48	1		T178	1		T215	1
auto[1]	values[6]	values[7]	12	1			T6	1		T40	3		T12	1
auto[1]	values[7]	values[0]	21	1			T247	1		T264	1		T282	1
auto[1]	values[7]	values[1]	11	1			T179	2		T57	1		T249	2
auto[1]	values[7]	values[2]	10	1			T44	3		T68	1		T166	1
auto[1]	values[7]	values[3]	1	1			T170	1		-	-		-	-
auto[1]	values[7]	values[4]	11	1			T48	1		T218	2		T14	1
auto[1]	values[7]	values[5]	10	1			T234	1		T195	3		T268	2
auto[1]	values[7]	values[6]	13	1			T12	1		T42	2		T234	4
auto[1]	values[7]	values[7]	10	1			T300	1		T301	2		T302	1