Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1886

1

T1

9

T2

5

T5

7

auto[1]

1830

1

T1

9

T2

8

T5

11

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1903

1

T1

15

T5

18

T6

8

auto[1]

1813

1

T1

3

T2

13

T32

18

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2975

1

T1

11

T2

13

T5

12

auto[1]

741

1

T1

7

T5

6

T6

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	741	1			T1	4		T2	2		T5	3
valid[1]	703	1			T1	3		T2	4		T5	3
valid[2]	773	1			T1	4		T2	1		T5	5
valid[3]	765	1			T1	3		T2	3		T5	4
valid[4]	734	1			T1	4		T2	3		T5	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	125	1			T5	1		T6	1		T33	2
auto[0]	auto[0]	valid[0]	auto[1]	169	1			T32	3		T12	2		T24	2
auto[0]	auto[0]	valid[1]	auto[0]	107	1			T1	1		T5	2		T33	1
auto[0]	auto[0]	valid[1]	auto[1]	191	1			T2	1		T32	1		T24	2
auto[0]	auto[0]	valid[2]	auto[0]	109	1			T1	1		T5	1		T33	1
auto[0]	auto[0]	valid[2]	auto[1]	183	1			T1	1		T12	1		T22	2
auto[0]	auto[0]	valid[3]	auto[0]	123	1			T1	1		T12	2		T44	1
auto[0]	auto[0]	valid[3]	auto[1]	197	1			T2	1		T32	1		T22	1
auto[0]	auto[0]	valid[4]	auto[0]	121	1			T1	2		T6	1		T23	1
auto[0]	auto[0]	valid[4]	auto[1]	185	1			T2	3		T32	2		T35	1
auto[0]	auto[1]	valid[0]	auto[0]	111	1			T1	1		T5	1		T6	1
auto[0]	auto[1]	valid[0]	auto[1]	165	1			T2	2		T32	4		T24	1
auto[0]	auto[1]	valid[1]	auto[0]	99	1			T1	1		T5	1		T33	1
auto[0]	auto[1]	valid[1]	auto[1]	180	1			T1	1		T2	3		T32	2
auto[0]	auto[1]	valid[2]	auto[0]	135	1			T5	3		T35	1		T12	1
auto[0]	auto[1]	valid[2]	auto[1]	191	1			T1	1		T2	1		T32	4
auto[0]	auto[1]	valid[3]	auto[0]	111	1			T1	1		T5	2		T12	1
auto[0]	auto[1]	valid[3]	auto[1]	181	1			T2	2		T32	1		T24	3
auto[0]	auto[1]	valid[4]	auto[0]	121	1			T5	1		T6	1		T12	2
auto[0]	auto[1]	valid[4]	auto[1]	171	1			T22	1		T24	2		T29	1
auto[1]	auto[0]	valid[0]	auto[0]	82	1			T1	2		T5	1		T33	1
auto[1]	auto[0]	valid[1]	auto[0]	63	1			T12	1		T23	2		T42	1
auto[1]	auto[0]	valid[2]	auto[0]	80	1			T12	1		T23	1		T28	1
auto[1]	auto[0]	valid[3]	auto[0]	75	1			T1	1		T5	1		T12	2
auto[1]	auto[0]	valid[4]	auto[0]	76	1			T5	1		T6	1		T12	2
auto[1]	auto[1]	valid[0]	auto[0]	89	1			T1	1		T6	1		T12	2
auto[1]	auto[1]	valid[1]	auto[0]	63	1			T6	1		T35	1		T12	1
auto[1]	auto[1]	valid[2]	auto[0]	75	1			T1	1		T5	1		T33	1
auto[1]	auto[1]	valid[3]	auto[0]	78	1			T5	1		T6	1		T23	1
auto[1]	auto[1]	valid[4]	auto[0]	60	1			T1	2		T5	1		T33	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal