Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	849	1			T13	11		T68	7		T14	4
all_values[1]	849	1			T13	11		T68	7		T14	4
all_values[2]	849	1			T13	11		T68	7		T14	4
all_values[3]	849	1			T13	11		T68	7		T14	4
all_values[4]	849	1			T13	11		T68	7		T14	4
all_values[5]	849	1			T13	11		T68	7		T14	4
all_values[6]	849	1			T13	11		T68	7		T14	4
all_values[7]	849	1			T13	11		T68	7		T14	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3617

1

T13

39

T68

34

T14

21

auto[1]

3175

1

T13

49

T68

22

T14

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2696

1

T13

36

T68

32

T14

12

auto[1]

4096

1

T13

52

T68

24

T14

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3846

1

T13

53

T68

37

T14

18

auto[1]

2946

1

T13

35

T68

19

T14

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	163	1			T13	2		T68	1		T15	1
all_values[0]	auto[0]	auto[0]	auto[1]	75	1			T13	1		T68	1		T14	1
all_values[0]	auto[0]	auto[1]	auto[0]	157	1			T13	1		T68	3		T15	1
all_values[0]	auto[0]	auto[1]	auto[1]	90	1			T15	4		T16	3		T17	2
all_values[0]	auto[1]	auto[0]	auto[1]	216	1			T13	7		T68	2		T14	3
all_values[0]	auto[1]	auto[1]	auto[1]	148	1			T15	1		T16	6		T17	3
all_values[1]	auto[0]	auto[0]	auto[0]	176	1			T13	4		T68	3		T15	3
all_values[1]	auto[0]	auto[0]	auto[1]	72	1			T13	1		T68	1		T17	1
all_values[1]	auto[0]	auto[1]	auto[0]	161	1			T13	3		T68	2		T14	2
all_values[1]	auto[0]	auto[1]	auto[1]	81	1			T15	4		T16	2		T17	1
all_values[1]	auto[1]	auto[0]	auto[1]	188	1			T13	1		T14	2		T15	2
all_values[1]	auto[1]	auto[1]	auto[1]	171	1			T13	2		T68	1		T15	5
all_values[2]	auto[0]	auto[0]	auto[0]	178	1			T68	2		T15	5		T16	3
all_values[2]	auto[0]	auto[0]	auto[1]	89	1			T13	1		T14	1		T16	2
all_values[2]	auto[0]	auto[1]	auto[0]	137	1			T13	5		T68	1		T15	2
all_values[2]	auto[0]	auto[1]	auto[1]	80	1			T13	1		T14	2		T15	2
all_values[2]	auto[1]	auto[0]	auto[1]	224	1			T13	4		T68	3		T14	1
all_values[2]	auto[1]	auto[1]	auto[1]	141	1			T68	1		T15	4		T16	1
all_values[3]	auto[0]	auto[0]	auto[0]	179	1			T13	1		T68	3		T14	1
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T13	1		T15	1		T16	1
all_values[3]	auto[0]	auto[1]	auto[0]	137	1			T15	2		T20	1		T59	5
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T13	4		T68	1		T14	1
all_values[3]	auto[1]	auto[0]	auto[1]	202	1			T13	1		T68	3		T14	1
all_values[3]	auto[1]	auto[1]	auto[1]	177	1			T13	4		T14	1		T15	1
all_values[4]	auto[0]	auto[0]	auto[0]	168	1			T68	4		T14	2		T16	1
all_values[4]	auto[0]	auto[0]	auto[1]	81	1			T68	1		T15	3		T16	4
all_values[4]	auto[0]	auto[1]	auto[0]	158	1			T13	7		T68	1		T14	1
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T13	1		T15	1		T16	1
all_values[4]	auto[1]	auto[0]	auto[1]	194	1			T68	1		T14	1		T15	5
all_values[4]	auto[1]	auto[1]	auto[1]	176	1			T13	3		T15	3		T16	2
all_values[5]	auto[0]	auto[0]	auto[0]	258	1			T13	3		T68	2		T14	1
all_values[5]	auto[0]	auto[1]	auto[0]	231	1			T13	5		T68	4		T14	1
all_values[5]	auto[1]	auto[0]	auto[1]	192	1			T13	2		T14	1		T15	3
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T13	1		T68	1		T14	1
all_values[6]	auto[0]	auto[0]	auto[0]	151	1			T13	2		T68	1		T14	1
all_values[6]	auto[0]	auto[0]	auto[1]	80	1			T13	1		T14	1		T15	1
all_values[6]	auto[0]	auto[1]	auto[0]	152	1			T13	2		T68	2		T15	4
all_values[6]	auto[0]	auto[1]	auto[1]	95	1			T13	2		T15	1		T17	2
all_values[6]	auto[1]	auto[0]	auto[1]	179	1			T13	1		T68	2		T14	1
all_values[6]	auto[1]	auto[1]	auto[1]	192	1			T13	3		T68	2		T14	1
all_values[7]	auto[0]	auto[0]	auto[0]	163	1			T13	1		T68	2		T14	2
all_values[7]	auto[0]	auto[0]	auto[1]	101	1			T13	2		T15	1		T17	1
all_values[7]	auto[0]	auto[1]	auto[0]	127	1			T68	1		T14	1		T15	2
all_values[7]	auto[0]	auto[1]	auto[1]	80	1			T13	2		T68	1		T15	1
all_values[7]	auto[1]	auto[0]	auto[1]	206	1			T13	3		T68	2		T14	1
all_values[7]	auto[1]	auto[1]	auto[1]	172	1			T13	3		T68	1		T15	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal