Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47571

1

T1

287

T5

444

T6

264

auto[1]

18915

1

T1

49

T2

146

T32

130

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49230

1

T1

231

T2

146

T5

300

auto[1]

17256

1

T1

105

T5

144

T6

89

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34344	1			T1	174		T2	66		T5	225
others[1]	5581	1			T1	28		T2	19		T5	38
others[2]	5490	1			T1	31		T2	10		T5	39
others[3]	6437	1			T1	43		T2	19		T5	38
interest[1]	3603	1			T1	14		T2	5		T5	30
interest[4]	22469	1			T1	107		T2	42		T5	146
interest[64]	11031	1			T1	46		T2	27		T5	74

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15652	1			T1	97		T5	150		T6	89
auto[0]	auto[0]	others[1]	2548	1			T1	16		T5	26		T6	20
auto[0]	auto[0]	others[2]	2497	1			T1	15		T5	29		T6	13
auto[0]	auto[0]	others[3]	2887	1			T1	22		T5	26		T6	11
auto[0]	auto[0]	interest[1]	1654	1			T1	5		T5	14		T6	12
auto[0]	auto[0]	interest[4]	10201	1			T1	56		T5	89		T6	61
auto[0]	auto[0]	interest[64]	5077	1			T1	27		T5	55		T6	30
auto[0]	auto[1]	others[0]	9759	1			T1	26		T2	66		T32	78
auto[0]	auto[1]	others[1]	1609	1			T1	2		T2	19		T32	7
auto[0]	auto[1]	others[2]	1575	1			T1	6		T2	10		T32	6
auto[0]	auto[1]	others[3]	1829	1			T1	5		T2	19		T32	14
auto[0]	auto[1]	interest[1]	1018	1			T1	4		T2	5		T32	7
auto[0]	auto[1]	interest[4]	6458	1			T1	19		T2	42		T32	51
auto[0]	auto[1]	interest[64]	3125	1			T1	6		T2	27		T32	18
auto[1]	auto[0]	others[0]	8933	1			T1	51		T5	75		T6	41
auto[1]	auto[0]	others[1]	1424	1			T1	10		T5	12		T6	6
auto[1]	auto[0]	others[2]	1418	1			T1	10		T5	10		T6	9
auto[1]	auto[0]	others[3]	1721	1			T1	16		T5	12		T6	11
auto[1]	auto[0]	interest[1]	931	1			T1	5		T5	16		T6	7
auto[1]	auto[0]	interest[4]	5810	1			T1	32		T5	57		T6	30
auto[1]	auto[0]	interest[64]	2829	1			T1	13		T5	19		T6	15

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal