Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2589666	1			T1	3558		T2	28550		T3	1
all_values[1]	2589666	1			T1	3558		T2	28550		T3	1
all_values[2]	2589666	1			T1	3558		T2	28550		T3	1
all_values[3]	2589666	1			T1	3558		T2	28550		T3	1
all_values[4]	2589666	1			T1	3558		T2	28550		T3	1
all_values[5]	2589666	1			T1	3558		T2	28550		T3	1
all_values[6]	2589666	1			T1	3558		T2	28550		T3	1
all_values[7]	2589666	1			T1	3558		T2	28550		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20229475

1

T1

28464

T2

228400

T3

8

auto[1]

487853

1

T15

26662

T17

70

T18

58116

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20695327

1

T1

28464

T2

228318

T3

8

auto[1]

22001

1

T2

82

T5

360

T23

48

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2505683	1			T1	3558		T2	28478		T3	1
all_values[0]	auto[0]	auto[1]	9818	1			T2	72		T5	176		T23	30
all_values[0]	auto[1]	auto[0]	73393	1			T15	4363		T17	5		T19	5
all_values[0]	auto[1]	auto[1]	772	1			T15	79		T17	2		T18	2
all_values[1]	auto[0]	auto[0]	2524203	1			T1	3558		T2	28540		T3	1
all_values[1]	auto[0]	auto[1]	6038	1			T2	10		T5	148		T23	9
all_values[1]	auto[1]	auto[0]	58886	1			T15	4357		T17	7		T18	1
all_values[1]	auto[1]	auto[1]	539	1			T15	82		T17	1		T19	4
all_values[2]	auto[0]	auto[0]	2512234	1			T1	3558		T2	28550		T3	1
all_values[2]	auto[0]	auto[1]	2308	1			T5	36		T23	9		T14	1
all_values[2]	auto[1]	auto[0]	74746	1			T15	4358		T17	4		T18	14514
all_values[2]	auto[1]	auto[1]	378	1			T15	80		T17	4		T18	14
all_values[3]	auto[0]	auto[0]	2509990	1			T1	3558		T2	28550		T3	1
all_values[3]	auto[0]	auto[1]	227	1			T15	3		T17	6		T19	8
all_values[3]	auto[1]	auto[0]	79202	1			T15	4436		T17	4		T18	14525
all_values[3]	auto[1]	auto[1]	247	1			T15	9		T18	3		T19	3
all_values[4]	auto[0]	auto[0]	2500831	1			T1	3558		T2	28550		T3	1
all_values[4]	auto[0]	auto[1]	204	1			T15	5		T17	4		T117	4
all_values[4]	auto[1]	auto[0]	88404	1			T15	6		T17	6		T18	14525
all_values[4]	auto[1]	auto[1]	227	1			T15	9		T17	6		T18	1
all_values[5]	auto[0]	auto[0]	2558563	1			T1	3558		T2	28550		T3	1
all_values[5]	auto[0]	auto[1]	196	1			T15	2		T17	2		T18	2
all_values[5]	auto[1]	auto[0]	30721	1			T15	4441		T17	7		T18	1
all_values[5]	auto[1]	auto[1]	186	1			T15	1		T17	6		T18	1
all_values[6]	auto[0]	auto[0]	2543163	1			T1	3558		T2	28550		T3	1
all_values[6]	auto[0]	auto[1]	228	1			T15	6		T17	6		T18	1
all_values[6]	auto[1]	auto[0]	46083	1			T15	1		T17	6		T18	14525
all_values[6]	auto[1]	auto[1]	192	1			T15	6		T17	2		T18	2
all_values[7]	auto[0]	auto[0]	2555585	1			T1	3558		T2	28550		T3	1
all_values[7]	auto[0]	auto[1]	204	1			T15	7		T17	4		T18	5
all_values[7]	auto[1]	auto[0]	33640	1			T15	4433		T17	7		T19	8
all_values[7]	auto[1]	auto[1]	237	1			T15	1		T17	3		T18	2