Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	30239	1			T1	115		T2	87		T5	118
auto[SpiFlashAddrCfg]	6095	1			T1	37		T2	52		T3	1
auto[SpiFlashAddr3b]	7378	1			T1	44		T2	47		T5	30
auto[SpiFlashAddr4b]	6164	1			T1	23		T2	42		T5	41

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28283

1

T1

117

T2

136

T3

1

auto[1]

21593

1

T1

102

T2

92

T5

111

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27164

1

T1

103

T2

128

T5

110

auto[1]

22712

1

T1

116

T2

100

T3

1

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	34118	1			T1	120		T2	102		T5	134
values[1]	894	1			T1	6		T2	8		T5	3
values[2]	1109	1			T1	3		T2	5		T5	8
values[3]	1156	1			T1	2		T2	13		T5	3
values[4]	1147	1			T1	14		T2	13		T3	1
values[5]	1154	1			T1	8		T2	10		T5	2
values[6]	1161	1			T1	9		T2	7		T5	8
values[7]	1194	1			T1	5		T2	15		T5	7
values[8]	7943	1			T1	52		T2	55		T5	43

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21844

1

T1

219

T2

228

T5

216

auto[1]

28032

1

T3

1

T11

1

T23

227

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

47210

1

T1

213

T2

217

T3

1

write

2666

1

T1

6

T2

11

T5

12

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15502

1

T1

80

T2

119

T5

79

valids[0x1]

34374

1

T1

139

T2

109

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1243	1			T1	7		T2	6		T5	6
internal_process_ops[0x5a]	1330	1			T1	5		T2	5		T5	5
internal_process_ops[0x05]	18919	1			T1	63		T2	15		T5	62
internal_process_ops[0x35]	1291	1			T1	5		T2	10		T5	5
internal_process_ops[0x15]	1231	1			T1	6		T2	6		T5	8
internal_process_ops[0x03]	857	1			T1	1		T2	9		T5	5
internal_process_ops[0x0b]	838	1			T1	7		T2	8		T3	1
internal_process_ops[0x3b]	799	1			T1	2		T2	5		T5	4
internal_process_ops[0x6b]	806	1			T1	3		T2	6		T5	3
internal_process_ops[0xbb]	830	1			T1	12		T2	11		T5	6
internal_process_ops[0xeb]	802	1			T1	5		T2	9		T5	9

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48571

1

T1

214

T2

224

T3

1

auto[1]

1305

1

T1

5

T2

4

T5

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48089

1

T1

212

T2

222

T3

1

auto[1]

1787

1

T1

7

T2

6

T5

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7264

1

T1

62

T2

57

T5

44

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4358

1

T1

51

T2

28

T5

69

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1509

1

T1

22

T2

21

T5

14

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1290

1

T1

14

T2

27

T5

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1877

1

T1

20

T2

31

T5

16

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1522

1

T1

23

T2

15

T5

9

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1652

1

T1

11

T2

20

T5

22

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1226

1

T1

10

T2

18

T5

18

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

94

1

T2

1

T5

4

T7

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

62

1

T2

1

T5

1

T12

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

43

1

T46

1

T44

4

T142

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

68

1

T1

2

T45

2

T47

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

100

1

T2

1

T7

4

T12

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

77

1

T2

1

T14

1

T46

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

56

1

T2

1

T46

1

T44

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

63

1

T1

1

T2

1

T5

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

90

1

T5

3

T12

1

T46

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

58

1

T1

1

T14

1

T60

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

44

1

T5

1

T143

1

T60

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

76

1

T2

1

T5

1

T12

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

77

1

T1

1

T2

3

T5

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

82

1

T44

1

T144

1

T60

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

76

1

T2

1

T143

1

T60

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

80

1

T1

1

T10

2

T12

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10280

1

T23

63

T41

6

T15

39

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7701

1

T23

33

T41

2

T15

25

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1333

1

T3

1

T23

16

T41

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1304

1

T23

17

T41

4

T15

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1684

1

T23

21

T41

6

T15

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1626

1

T23

25

T41

1

T15

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1267

1

T11

1

T23

14

T15

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1317

1

T23

23

T15

9

T43

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

99

1

T16

2

T145

1

T18

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

95

1

T15

1

T146

1

T18

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

91

1

T146

1

T145

2

T18

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

84

1

T16

1

T145

1

T18

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

93

1

T146

1

T145

3

T18

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

94

1

T15

2

T68

1

T18

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

81

1

T15

3

T145

1

T18

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

95

1

T23

4

T15

2

T16

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

120

1

T23

1

T15

1

T18

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

93

1

T23

1

T16

2

T18

7

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

93

1

T15

1

T146

1

T145

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

95

1

T23

2

T15

1

T16

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

102

1

T15

2

T146

2

T145

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

81

1

T23

2

T145

1

T18

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

102

1

T23

2

T68

1

T18

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

102

1

T23

3

T43

1

T16

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	2825	1			T1	25		T2	41		T5	29
auto[0]	values[0]	valids[0x1]	10862	1			T1	95		T2	61		T5	105
auto[0]	values[1]	valids[0x1]	427	1			T1	6		T2	8		T5	3
auto[0]	values[2]	valids[0x0]	333	1			T1	3		T2	5		T5	4
auto[0]	values[2]	valids[0x1]	226	1			T5	4		T12	2		T14	4
auto[0]	values[3]	valids[0x0]	371	1			T2	10		T5	2		T12	7
auto[0]	values[3]	valids[0x1]	203	1			T1	2		T2	3		T5	1
auto[0]	values[4]	valids[0x0]	387	1			T1	10		T2	8		T5	4
auto[0]	values[4]	valids[0x1]	216	1			T1	4		T2	5		T5	4
auto[0]	values[5]	valids[0x0]	391	1			T1	4		T2	5		T5	2
auto[0]	values[5]	valids[0x1]	201	1			T1	4		T2	5		T12	3
auto[0]	values[6]	valids[0x0]	365	1			T1	7		T2	4		T5	7
auto[0]	values[6]	valids[0x1]	234	1			T1	2		T2	3		T5	1
auto[0]	values[7]	valids[0x0]	428	1			T1	4		T2	7		T5	4
auto[0]	values[7]	valids[0x1]	204	1			T1	1		T2	8		T5	3
auto[0]	values[8]	valids[0x0]	2586	1			T1	27		T2	39		T5	27
auto[0]	values[8]	valids[0x1]	1585	1			T1	25		T2	16		T5	16
auto[1]	values[0]	valids[0x0]	3571	1			T23	42		T41	8		T15	10
auto[1]	values[0]	valids[0x1]	16860	1			T23	75		T41	2		T15	63
auto[1]	values[1]	valids[0x1]	467	1			T23	11		T15	5		T43	1
auto[1]	values[2]	valids[0x0]	336	1			T23	6		T15	1		T16	1
auto[1]	values[2]	valids[0x1]	214	1			T23	6		T15	2		T43	1
auto[1]	values[3]	valids[0x0]	320	1			T41	2		T15	2		T43	3
auto[1]	values[3]	valids[0x1]	262	1			T23	2		T15	1		T43	2
auto[1]	values[4]	valids[0x0]	338	1			T23	4		T15	5		T43	3
auto[1]	values[4]	valids[0x1]	206	1			T3	1		T23	4		T16	1
auto[1]	values[5]	valids[0x0]	330	1			T15	2		T43	2		T16	3
auto[1]	values[5]	valids[0x1]	232	1			T23	1		T41	1		T15	2
auto[1]	values[6]	valids[0x0]	350	1			T23	6		T15	1		T68	6
auto[1]	values[6]	valids[0x1]	212	1			T23	2		T43	1		T68	1
auto[1]	values[7]	valids[0x0]	334	1			T23	9		T41	2		T43	1
auto[1]	values[7]	valids[0x1]	228	1			T23	3		T41	1		T146	6
auto[1]	values[8]	valids[0x0]	2237	1			T23	41		T41	1		T15	11
auto[1]	values[8]	valids[0x1]	1535	1			T11	1		T23	15		T41	3