Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2735740

1

T1

6490

T2

20083

T3

2

auto[1]

17582

1

T1

59

T2

8

T5

56

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

800673

1

T1

40

T2

53

T3

2

auto[1]

1952649

1

T1

6509

T2

20038

T5

9611

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	544632	1			T1	5		T2	271		T3	2
auto[524288:1048575]	354900	1			T1	134		T2	135		T5	525
auto[1048576:1572863]	326418	1			T1	3		T2	4390		T5	1733
auto[1572864:2097151]	303049	1			T1	9		T2	9466		T5	287
auto[2097152:2621439]	313441	1			T1	2862		T2	259		T5	27
auto[2621440:3145727]	323024	1			T1	3094		T2	2871		T5	6
auto[3145728:3670015]	314769	1			T1	276		T2	271		T5	4283
auto[3670016:4194303]	273089	1			T1	166		T2	2428		T5	1

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1971244

1

T1

6544

T2

20091

T3

2

auto[1]

782078

1

T1

5

T5

1

T7

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2394085

1

T1

5851

T2

17475

T3

2

auto[1]

359237

1

T1

698

T2

2616

T5

4546

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	229662	1			T1	2		T2	4		T3	2
auto[0]	auto[0]	auto[0:524287]	auto[1]	270434	1			T1	1		T2	262		T5	2789
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	86858	1			T1	3		T5	8		T9	93
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	216953	1			T1	131		T2	128		T12	256
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	105834	1			T2	6		T5	7		T8	59
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	171583	1			T2	4382		T5	1715		T12	1471
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	86535	1			T1	3		T2	3		T5	6
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	181471	1			T1	1		T2	6865		T5	264
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	78450	1			T1	5		T2	3		T5	9
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	185019	1			T1	2460		T2	256		T5	7
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	67904	1			T1	4		T2	2		T5	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	197451	1			T1	3073		T2	2868		T5	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	68077	1			T2	9		T5	1		T9	65
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	195943	1			T2	258		T5	257		T12	705
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	62734	1			T1	5		T2	3		T5	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	175211	1			T1	130		T2	2420		T23	129
auto[0]	auto[1]	auto[0:524287]	auto[0]	1574	1			T2	1		T23	1		T14	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	39985	1			T2	1		T14	129		T46	2991
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	880	1			T2	5		T5	5		T23	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	48472	1			T2	1		T5	512		T23	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	3930	1			T1	3		T2	2		T12	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	42799	1			T23	260		T24	640		T143	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1290	1			T2	2		T5	1		T46	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	31789	1			T2	2595		T5	1		T46	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	294	1			T1	4		T23	2		T24	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	47546	1			T1	393		T23	1883		T61	2450
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2548	1			T2	1		T23	1		T14	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	53023	1			T23	4		T43	948		T16	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1234	1			T1	2		T2	1		T5	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	47442	1			T1	262		T5	4018		T12	2347
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1078	1			T1	2		T2	5		T23	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	31737	1			T1	6		T23	2641		T142	514
auto[1]	auto[0]	auto[0:524287]	auto[0]	237	1			T1	1		T2	1		T5	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	2125	1			T1	1		T2	1		T5	11
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	167	1			T43	2		T46	2		T16	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1267	1			T43	18		T16	64		T44	10
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	182	1			T5	2		T12	2		T23	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1616	1			T5	9		T12	31		T23	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	170	1			T1	1		T2	1		T5	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1414	1			T1	4		T5	9		T14	54
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	184	1			T5	3		T12	1		T14	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1538	1			T5	8		T12	4		T14	13
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	179	1			T1	1		T12	1		T24	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1457	1			T1	16		T12	1		T24	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	178	1			T2	2		T5	1		T12	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1499	1			T2	1		T5	1		T12	36
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	154	1			T1	2		T23	1		T16	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1599	1			T1	7		T16	44		T142	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	45	1			T2	1		T14	1		T61	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	570	1			T14	27		T61	1		T20	22
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	32	1			T2	1		T16	1		T143	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	271	1			T16	4		T143	1		T60	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	42	1			T23	1		T127	2		T154	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	432	1			T23	1		T127	23		T216	20
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	46	1			T5	1		T145	1		T61	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	334	1			T5	3		T18	15		T20	22
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	34	1			T61	2		T18	2		T35	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	376	1			T61	2		T18	85		T154	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	58	1			T16	2		T60	1		T145	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	404	1			T16	6		T60	2		T145	10
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	31	1			T1	1		T5	1		T12	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	365	1			T1	11		T5	2		T12	36
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	52	1			T1	1		T142	2		T19	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	524	1			T1	13		T142	15		T20	54

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1608993	1			T1	5816		T2	17469		T3	2
auto[0]	auto[0]	auto[1]	771126	1			T1	2		T5	1		T7	1
auto[0]	auto[1]	auto[0]	345058	1			T1	672		T2	2614		T5	4539
auto[0]	auto[1]	auto[1]	10563	1			T12	1		T14	1		T16	1
auto[1]	auto[0]	auto[0]	13632	1			T1	30		T2	6		T5	49
auto[1]	auto[0]	auto[1]	334	1			T1	3		T7	2		T12	4
auto[1]	auto[1]	auto[0]	3561	1			T1	26		T2	2		T5	7
auto[1]	auto[1]	auto[1]	55	1			T12	1		T14	1		T18	1