Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12942

1

T1

117

T2

136

T5

105

auto[1]

8902

1

T1

102

T2

92

T5

111

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2814	1			T1	25		T2	102		T5	20
values[1]	2786	1			T1	29		T2	21		T5	85
values[2]	2485	1			T1	40		T10	12		T12	20
values[3]	2766	1			T1	71		T12	110		T14	71
values[4]	3352	1			T2	21		T5	65		T12	40
values[5]	2280	1			T1	34		T2	20		T14	49
values[6]	2531	1			T1	20		T5	46		T8	6
values[7]	2830	1			T2	64		T9	4		T12	59

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2996	1			T2	44		T12	79		T24	33
values[1]	2576	1			T1	137		T2	40		T8	6
values[2]	2570	1			T29	12		T191	14		T46	28
values[3]	3627	1			T1	37		T2	20		T5	65
values[4]	2467	1			T1	45		T2	20		T5	46
values[5]	2411	1			T2	41		T24	51		T14	48
values[6]	2801	1			T2	43		T5	40		T74	2
values[7]	2396	1			T2	20		T5	65		T12	45

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	253	1			T142	24		T62	12		T186	13
auto[0]	values[0]	values[1]	193	1			T2	25		T30	10		T14	5
auto[0]	values[0]	values[2]	156	1			T158	8		T217	10		T218	15
auto[0]	values[0]	values[3]	191	1			T24	13		T14	12		T46	16
auto[0]	values[0]	values[4]	199	1			T1	17		T219	12		T127	44
auto[0]	values[0]	values[5]	165	1			T2	11		T24	12		T60	11
auto[0]	values[0]	values[6]	259	1			T2	9		T5	14		T14	10
auto[0]	values[0]	values[7]	198	1			T2	10		T12	15		T14	30
auto[0]	values[1]	values[0]	236	1			T44	15		T220	18		T20	37
auto[0]	values[1]	values[1]	186	1			T1	23		T44	11		T221	10
auto[0]	values[1]	values[2]	154	1			T222	10		T176	14		T218	55
auto[0]	values[1]	values[3]	391	1			T5	7		T207	4		T60	4
auto[0]	values[1]	values[4]	256	1			T7	63		T164	73		T127	12
auto[0]	values[1]	values[5]	128	1			T2	12		T14	8		T223	6
auto[0]	values[1]	values[6]	119	1			T28	10		T38	8		T44	10
auto[0]	values[1]	values[7]	222	1			T5	23		T46	16		T44	5
auto[0]	values[2]	values[0]	179	1			T142	14		T60	8		T61	9
auto[0]	values[2]	values[1]	88	1			T1	20		T60	10		T224	2
auto[0]	values[2]	values[2]	230	1			T144	31		T127	11		T128	14
auto[0]	values[2]	values[3]	206	1			T12	9		T213	22		T174	14
auto[0]	values[2]	values[4]	161	1			T44	41		T225	10		T20	21
auto[0]	values[2]	values[5]	203	1			T189	18		T198	11		T226	6
auto[0]	values[2]	values[6]	175	1			T74	2		T46	15		T127	14
auto[0]	values[2]	values[7]	144	1			T227	8		T62	10		T186	12
auto[0]	values[3]	values[0]	197	1			T12	13		T14	42		T20	13
auto[0]	values[3]	values[1]	309	1			T1	12		T14	17		T61	16
auto[0]	values[3]	values[2]	208	1			T46	16		T198	8		T228	8
auto[0]	values[3]	values[3]	192	1			T1	8		T20	27		T229	4
auto[0]	values[3]	values[4]	112	1			T12	6		T75	4		T61	15
auto[0]	values[3]	values[5]	227	1			T143	17		T60	13		T208	22
auto[0]	values[3]	values[6]	119	1			T168	13		T205	11		T201	13
auto[0]	values[3]	values[7]	142	1			T174	11		T209	4		T230	16
auto[0]	values[4]	values[0]	244	1			T198	13		T71	12		T231	8
auto[0]	values[4]	values[1]	238	1			T232	6		T142	12		T60	34
auto[0]	values[4]	values[2]	234	1			T20	11		T233	15		T173	14
auto[0]	values[4]	values[3]	624	1			T5	15		T144	12		T20	73
auto[0]	values[4]	values[4]	156	1			T5	13		T12	14		T44	14
auto[0]	values[4]	values[5]	111	1			T24	21		T60	9		T61	12
auto[0]	values[4]	values[6]	339	1			T2	19		T46	7		T234	6
auto[0]	values[4]	values[7]	169	1			T12	7		T235	10		T44	15
auto[0]	values[5]	values[0]	173	1			T44	12		T144	11		T60	6
auto[0]	values[5]	values[1]	145	1			T1	21		T60	23		T181	26
auto[0]	values[5]	values[2]	180	1			T61	15		T236	24		T175	11
auto[0]	values[5]	values[3]	180	1			T2	11		T20	21		T62	16
auto[0]	values[5]	values[4]	165	1			T176	13		T237	6		T238	4
auto[0]	values[5]	values[5]	151	1			T144	14		T204	12		T176	19
auto[0]	values[5]	values[6]	377	1			T14	40		T44	11		T144	59
auto[0]	values[5]	values[7]	91	1			T195	18		T239	25		T240	10
auto[0]	values[6]	values[0]	143	1			T46	18		T241	16		T190	17
auto[0]	values[6]	values[1]	189	1			T8	6		T61	15		T242	4
auto[0]	values[6]	values[2]	293	1			T191	14		T142	34		T61	14
auto[0]	values[6]	values[3]	313	1			T62	20		T186	11		T243	6
auto[0]	values[6]	values[4]	147	1			T1	16		T5	20		T76	4
auto[0]	values[6]	values[5]	186	1			T80	10		T143	12		T244	4
auto[0]	values[6]	values[6]	221	1			T5	13		T44	13		T144	13
auto[0]	values[6]	values[7]	100	1			T127	6		T168	12		T173	17
auto[0]	values[7]	values[0]	211	1			T2	29		T12	48		T24	10
auto[0]	values[7]	values[1]	258	1			T9	4		T121	14		T142	10
auto[0]	values[7]	values[2]	211	1			T29	12		T44	42		T245	28
auto[0]	values[7]	values[3]	135	1			T24	7		T60	11		T128	21
auto[0]	values[7]	values[4]	182	1			T2	10		T60	5		T168	7
auto[0]	values[7]	values[5]	137	1			T127	8		T183	24		T173	11
auto[0]	values[7]	values[6]	157	1			T127	32		T168	33		T173	10
auto[0]	values[7]	values[7]	284	1			T44	43		T246	7		T179	14
auto[1]	values[0]	values[0]	260	1			T142	16		T62	19		T186	40
auto[1]	values[0]	values[1]	235	1			T2	15		T14	42		T61	7
auto[1]	values[0]	values[2]	51	1			T247	2		T218	5		T248	12
auto[1]	values[0]	values[3]	136	1			T24	7		T14	8		T46	6
auto[1]	values[0]	values[4]	94	1			T1	8		T47	14		T127	20
auto[1]	values[0]	values[5]	147	1			T2	9		T24	8		T60	14
auto[1]	values[0]	values[6]	214	1			T2	13		T5	6		T14	38
auto[1]	values[0]	values[7]	63	1			T2	10		T12	10		T14	9
auto[1]	values[1]	values[0]	115	1			T44	10		T20	10		T127	5
auto[1]	values[1]	values[1]	129	1			T1	6		T44	9		T62	7
auto[1]	values[1]	values[2]	55	1			T176	6		T218	16		T249	11
auto[1]	values[1]	values[3]	312	1			T5	13		T60	25		T62	19
auto[1]	values[1]	values[4]	97	1			T127	22		T168	11		T173	13
auto[1]	values[1]	values[5]	101	1			T2	9		T14	40		T173	10
auto[1]	values[1]	values[6]	87	1			T44	38		T250	14		T37	26
auto[1]	values[1]	values[7]	198	1			T5	42		T46	5		T44	15
auto[1]	values[2]	values[0]	164	1			T142	6		T60	12		T61	17
auto[1]	values[2]	values[1]	91	1			T1	20		T10	12		T60	10
auto[1]	values[2]	values[2]	203	1			T144	21		T127	12		T128	6
auto[1]	values[2]	values[3]	76	1			T12	11		T174	6		T246	9
auto[1]	values[2]	values[4]	230	1			T44	4		T20	30		T195	15
auto[1]	values[2]	values[5]	94	1			T198	18		T251	9		T252	6
auto[1]	values[2]	values[6]	131	1			T46	5		T127	8		T253	10
auto[1]	values[2]	values[7]	110	1			T227	15		T62	11		T186	8
auto[1]	values[3]	values[0]	160	1			T12	7		T14	7		T20	7
auto[1]	values[3]	values[1]	139	1			T1	22		T14	5		T61	4
auto[1]	values[3]	values[2]	101	1			T46	12		T198	12		T175	9
auto[1]	values[3]	values[3]	103	1			T1	29		T20	17		T195	10
auto[1]	values[3]	values[4]	189	1			T12	84		T61	5		T198	56
auto[1]	values[3]	values[5]	171	1			T143	8		T60	9		T205	4
auto[1]	values[3]	values[6]	93	1			T168	7		T205	9		T201	7
auto[1]	values[3]	values[7]	304	1			T254	14		T174	11		T252	59
auto[1]	values[4]	values[0]	181	1			T198	8		T168	42		T169	24
auto[1]	values[4]	values[1]	94	1			T142	15		T60	19		T205	14
auto[1]	values[4]	values[2]	170	1			T255	16		T20	9		T233	5
auto[1]	values[4]	values[3]	261	1			T5	30		T144	8		T20	10
auto[1]	values[4]	values[4]	92	1			T5	7		T12	6		T44	22
auto[1]	values[4]	values[5]	137	1			T24	10		T60	11		T61	9
auto[1]	values[4]	values[6]	241	1			T2	2		T46	13		T175	7
auto[1]	values[4]	values[7]	61	1			T12	13		T44	5		T62	9
auto[1]	values[5]	values[0]	156	1			T44	8		T144	11		T60	18
auto[1]	values[5]	values[1]	89	1			T1	13		T60	2		T181	16
auto[1]	values[5]	values[2]	64	1			T61	5		T175	9		T181	10
auto[1]	values[5]	values[3]	78	1			T2	9		T20	10		T180	14
auto[1]	values[5]	values[4]	99	1			T176	16		T256	6		T257	49
auto[1]	values[5]	values[5]	175	1			T45	2		T144	6		T176	88
auto[1]	values[5]	values[6]	108	1			T14	9		T44	9		T144	10
auto[1]	values[5]	values[7]	49	1			T195	3		T239	28		T240	10
auto[1]	values[6]	values[0]	49	1			T46	7		T241	4		T190	7
auto[1]	values[6]	values[1]	88	1			T61	14		T176	4		T175	7
auto[1]	values[6]	values[2]	150	1			T142	5		T61	8		T193	9
auto[1]	values[6]	values[3]	281	1			T62	4		T186	9		T175	7
auto[1]	values[6]	values[4]	73	1			T1	4		T5	6		T205	13
auto[1]	values[6]	values[5]	100	1			T143	10		T20	14		T198	11
auto[1]	values[6]	values[6]	86	1			T5	7		T44	7		T144	7
auto[1]	values[6]	values[7]	112	1			T127	35		T168	16		T173	8
auto[1]	values[7]	values[0]	275	1			T2	15		T12	11		T24	23
auto[1]	values[7]	values[1]	105	1			T142	10		T144	5		T258	5
auto[1]	values[7]	values[2]	110	1			T44	27		T258	7		T202	19
auto[1]	values[7]	values[3]	148	1			T24	13		T60	11		T128	1
auto[1]	values[7]	values[4]	215	1			T2	10		T60	21		T259	6
auto[1]	values[7]	values[5]	178	1			T127	44		T183	9		T173	9
auto[1]	values[7]	values[6]	75	1			T127	12		T168	7		T173	10
auto[1]	values[7]	values[7]	149	1			T44	11		T246	13		T218	6