Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2589666	1			T1	3558		T2	28550		T3	1
all_pins[1]	2589666	1			T1	3558		T2	28550		T3	1
all_pins[2]	2589666	1			T1	3558		T2	28550		T3	1
all_pins[3]	2589666	1			T1	3558		T2	28550		T3	1
all_pins[4]	2589666	1			T1	3558		T2	28550		T3	1
all_pins[5]	2589666	1			T1	3558		T2	28550		T3	1
all_pins[6]	2589666	1			T1	3558		T2	28550		T3	1
all_pins[7]	2589666	1			T1	3558		T2	28550		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20668268	1			T1	28464		T2	228400		T3	8
values[0x1]	49060	1			T15	557		T17	24		T18	14493
transitions[0x0=>0x1]	48021	1			T15	387		T17	21		T18	14486
transitions[0x1=>0x0]	48031	1			T15	387		T17	21		T18	14486

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2588850	1			T1	3558		T2	28550		T3	1
all_pins[0]	values[0x1]	816	1			T15	85		T17	2		T18	2
all_pins[0]	transitions[0x0=>0x1]	460	1			T15	4		T17	2		T18	2
all_pins[0]	transitions[0x1=>0x0]	208	1			T15	7		T17	1		T19	3
all_pins[1]	values[0x0]	2589102	1			T1	3558		T2	28550		T3	1
all_pins[1]	values[0x1]	564	1			T15	88		T17	1		T19	4
all_pins[1]	transitions[0x0=>0x1]	350	1			T15	9		T19	2		T20	19
all_pins[1]	transitions[0x1=>0x0]	180	1			T15	5		T17	3		T18	17
all_pins[2]	values[0x0]	2589272	1			T1	3558		T2	28550		T3	1
all_pins[2]	values[0x1]	394	1			T15	84		T17	4		T18	17
all_pins[2]	transitions[0x0=>0x1]	322	1			T15	79		T17	4		T18	14
all_pins[2]	transitions[0x1=>0x0]	175	1			T15	4		T19	3		T20	8
all_pins[3]	values[0x0]	2589419	1			T1	3558		T2	28550		T3	1
all_pins[3]	values[0x1]	247	1			T15	9		T18	3		T19	3
all_pins[3]	transitions[0x0=>0x1]	180	1			T15	6		T18	3		T19	1
all_pins[3]	transitions[0x1=>0x0]	160	1			T15	6		T17	6		T18	1
all_pins[4]	values[0x0]	2589439	1			T1	3558		T2	28550		T3	1
all_pins[4]	values[0x1]	227	1			T15	9		T17	6		T18	1
all_pins[4]	transitions[0x0=>0x1]	182	1			T15	8		T17	4		T18	1
all_pins[4]	transitions[0x1=>0x0]	686	1			T15	274		T17	4		T18	1
all_pins[5]	values[0x0]	2588935	1			T1	3558		T2	28550		T3	1
all_pins[5]	values[0x1]	731	1			T15	275		T17	6		T18	1
all_pins[5]	transitions[0x0=>0x1]	575	1			T15	275		T17	6		T19	4
all_pins[5]	transitions[0x1=>0x0]	45688	1			T15	6		T17	2		T18	14466
all_pins[6]	values[0x0]	2543822	1			T1	3558		T2	28550		T3	1
all_pins[6]	values[0x1]	45844	1			T15	6		T17	2		T18	14467
all_pins[6]	transitions[0x0=>0x1]	45785	1			T15	5		T17	2		T18	14465
all_pins[6]	transitions[0x1=>0x0]	178	1			T17	3		T19	3		T20	6
all_pins[7]	values[0x0]	2589429	1			T1	3558		T2	28550		T3	1
all_pins[7]	values[0x1]	237	1			T15	1		T17	3		T18	2
all_pins[7]	transitions[0x0=>0x1]	167	1			T15	1		T17	3		T18	1
all_pins[7]	transitions[0x1=>0x0]	756	1			T15	85		T17	2		T18	1