Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	339	1			T1	4		T2	2		T5	2
auto[ReadAddrCrossIntoMailbox]	206	1			T1	1		T2	1		T5	1
auto[ReadAddrCrossOutOfMailbox]	224	1			T2	1		T5	4		T12	8
auto[ReadAddrCrossAllMailbox]	182	1			T2	1		T5	1		T12	1
auto[ReadAddrOutsideMailbox]	2572	1			T1	25		T2	43		T5	25

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1750

1

T1

18

T2

29

T5

15

auto[1]

1773

1

T1

12

T2

19

T5

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	615	1			T1	1		T2	9		T5	5
read_ops[0x0b]	619	1			T1	7		T2	8		T5	6
read_ops[0x3b]	549	1			T1	2		T2	5		T5	4
read_ops[0x6b]	565	1			T1	3		T2	6		T5	3
read_ops[0xbb]	606	1			T1	12		T2	11		T5	6
read_ops[0xeb]	569	1			T1	5		T2	9		T5	9

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T5	1		T14	1		T44	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T1	1		T46	1		T44	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T44	1		T20	1		T62	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T44	1		T205	1		T246	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T5	1		T12	2		T24	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	13	1			T24	1		T44	1		T198	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T20	1		T227	1		T181	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T24	1		T175	1		T260	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	217	1			T2	6		T5	2		T12	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	247	1			T2	3		T5	1		T12	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T1	1		T30	1		T244	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T1	1		T12	1		T30	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T44	1		T198	1		T174	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T2	1		T46	1		T44	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T220	1		T127	1		T227	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T12	2		T24	1		T44	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T220	1		T61	1		T20	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T2	1		T5	1		T12	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	218	1			T1	4		T2	4		T24	6
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	223	1			T1	1		T2	2		T5	5
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T5	1		T44	1		T220	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T14	1		T142	1		T220	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T5	1		T198	1		T127	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T1	1		T24	1		T20	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T44	1		T220	1		T60	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T5	1		T12	2		T220	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T220	1		T198	1		T213	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T220	1		T213	2		T202	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	174	1			T2	2		T5	1		T7	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	215	1			T1	1		T2	3		T7	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T2	1		T12	1		T14	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T12	1		T207	1		T46	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T24	1		T128	1		T173	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T142	2		T258	1		T205	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T60	2		T61	1		T168	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T227	1		T173	1		T195	3
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T60	2		T61	2		T20	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T198	1		T62	1		T249	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	213	1			T1	3		T2	4		T5	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	194	1			T2	1		T9	1		T10	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T30	1		T46	1		T127	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	18	1			T1	1		T30	1		T61	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T24	1		T144	1		T60	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T61	1		T213	1		T168	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T2	1		T5	1		T12	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T144	1		T20	3		T127	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T20	1		T127	1		T195	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T46	1		T44	1		T20	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	218	1			T1	7		T2	6		T5	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	237	1			T1	4		T2	4		T5	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T220	1		T198	1		T62	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T2	1		T46	1		T44	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	13	1			T20	1		T213	1		T168	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T14	1		T60	1		T20	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T5	1		T14	1		T198	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T12	1		T60	2		T20	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T62	1		T168	1		T261	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T127	1		T62	1		T261	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	218	1			T1	3		T2	5		T5	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	198	1			T1	2		T2	3		T5	7