Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3195	1			T1	79		T5	20		T12	59
values[1]	2342	1			T1	20		T2	42		T5	65
values[2]	2613	1			T1	37		T2	24		T5	86
values[3]	2128	1			T2	20		T7	63		T8	6
values[4]	2886	1			T1	54		T24	20		T191	14
values[5]	3392	1			T2	61		T24	20		T14	71
values[6]	2390	1			T2	20		T5	45		T10	12
values[7]	2898	1			T1	29		T2	61		T24	31

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2849	1			T1	34		T2	22		T14	20
values[1]	2029	1			T5	65		T12	20		T29	12
values[2]	3050	1			T1	57		T2	20		T9	4
values[3]	2746	1			T1	59		T2	21		T5	45
values[4]	2887	1			T1	29		T2	41		T8	6
values[5]	2673	1			T2	40		T5	46		T24	20
values[6]	2890	1			T2	40		T5	40		T7	63
values[7]	2720	1			T1	40		T2	44		T5	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21278

1

T1

214

T2

224

T5

213

auto[1]

566

1

T1

5

T2

4

T5

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	325	1			T1	33		T262	107		T127	31
auto[0]	values[0]	values[1]	223	1			T60	22		T221	10		T198	19
auto[0]	values[0]	values[2]	484	1			T44	40		T253	10		T187	110
auto[0]	values[0]	values[3]	411	1			T1	24		T12	58		T24	31
auto[0]	values[0]	values[4]	345	1			T46	25		T75	4		T61	25
auto[0]	values[0]	values[5]	296	1			T144	20		T173	20		T263	14
auto[0]	values[0]	values[6]	470	1			T5	20		T14	44		T255	14
auto[0]	values[0]	values[7]	570	1			T1	20		T235	10		T142	20
auto[0]	values[1]	values[0]	317	1			T2	22		T44	20		T72	10
auto[0]	values[1]	values[1]	140	1			T12	16		T232	6		T207	4
auto[0]	values[1]	values[2]	250	1			T1	20		T9	4		T12	20
auto[0]	values[1]	values[3]	263	1			T5	45		T20	29		T183	33
auto[0]	values[1]	values[4]	355	1			T12	44		T38	8		T219	12
auto[0]	values[1]	values[5]	401	1			T264	2		T168	22		T195	20
auto[0]	values[1]	values[6]	272	1			T2	20		T127	20		T62	24
auto[0]	values[1]	values[7]	266	1			T5	20		T127	19		T228	8
auto[0]	values[2]	values[0]	191	1			T127	40		T181	31		T246	23
auto[0]	values[2]	values[1]	188	1			T5	20		T60	21		T61	20
auto[0]	values[2]	values[2]	535	1			T1	36		T12	90		T121	14
auto[0]	values[2]	values[3]	300	1			T14	48		T61	23		T20	24
auto[0]	values[2]	values[4]	110	1			T180	14		T213	22		T243	6
auto[0]	values[2]	values[5]	474	1			T5	44		T158	8		T168	52
auto[0]	values[2]	values[6]	431	1			T5	19		T28	10		T46	19
auto[0]	values[2]	values[7]	328	1			T2	23		T61	21		T127	20
auto[0]	values[3]	values[0]	292	1			T189	18		T44	19		T60	26
auto[0]	values[3]	values[1]	142	1			T29	12		T144	20		T62	20
auto[0]	values[3]	values[2]	439	1			T30	10		T192	8		T206	4
auto[0]	values[3]	values[3]	163	1			T20	31		T127	51		T205	19
auto[0]	values[3]	values[4]	264	1			T8	6		T168	51		T237	6
auto[0]	values[3]	values[5]	188	1			T186	20		T229	4		T173	20
auto[0]	values[3]	values[6]	356	1			T7	63		T220	18		T144	62
auto[0]	values[3]	values[7]	243	1			T2	20		T216	42		T265	4
auto[0]	values[4]	values[0]	479	1			T44	20		T60	20		T168	59
auto[0]	values[4]	values[1]	373	1			T60	20		T223	6		T254	14
auto[0]	values[4]	values[2]	344	1			T143	21		T61	20		T127	24
auto[0]	values[4]	values[3]	373	1			T1	32		T142	20		T198	22
auto[0]	values[4]	values[4]	286	1			T46	28		T266	14		T267	14
auto[0]	values[4]	values[5]	339	1			T24	20		T191	14		T47	12
auto[0]	values[4]	values[6]	344	1			T244	4		T61	17		T128	22
auto[0]	values[4]	values[7]	258	1			T1	20		T44	44		T166	18
auto[0]	values[5]	values[0]	516	1			T60	22		T245	28		T175	30
auto[0]	values[5]	values[1]	319	1			T14	49		T143	25		T62	33
auto[0]	values[5]	values[2]	365	1			T2	19		T80	10		T44	72
auto[0]	values[5]	values[3]	412	1			T46	22		T164	73		T20	47
auto[0]	values[5]	values[4]	610	1			T2	39		T24	20		T14	21
auto[0]	values[5]	values[5]	326	1			T44	48		T20	83		T268	14
auto[0]	values[5]	values[6]	379	1			T46	20		T44	19		T142	19
auto[0]	values[5]	values[7]	376	1			T198	27		T193	25		T175	84
auto[0]	values[6]	values[0]	213	1			T20	20		T127	20		T62	20
auto[0]	values[6]	values[1]	412	1			T5	45		T14	47		T46	20
auto[0]	values[6]	values[2]	290	1			T12	19		T24	20		T175	26
auto[0]	values[6]	values[3]	464	1			T14	47		T44	60		T60	23
auto[0]	values[6]	values[4]	165	1			T10	10		T46	20		T198	66
auto[0]	values[6]	values[5]	201	1			T60	20		T199	10		T157	10
auto[0]	values[6]	values[6]	323	1			T2	20		T142	20		T69	8
auto[0]	values[6]	values[7]	264	1			T74	2		T143	20		T144	69
auto[0]	values[7]	values[0]	437	1			T14	20		T204	12		T190	22
auto[0]	values[7]	values[1]	181	1			T20	18		T198	17		T226	6
auto[0]	values[7]	values[2]	279	1			T24	28		T205	20		T246	20
auto[0]	values[7]	values[3]	305	1			T2	21		T144	53		T233	20
auto[0]	values[7]	values[4]	650	1			T1	29		T44	19		T142	25
auto[0]	values[7]	values[5]	386	1			T2	40		T173	20		T195	21
auto[0]	values[7]	values[6]	237	1			T198	20		T168	37		T269	2
auto[0]	values[7]	values[7]	340	1			T61	25		T20	20		T258	20
auto[1]	values[0]	values[0]	13	1			T1	1		T127	3		T181	1
auto[1]	values[0]	values[1]	3	1			T198	1		T252	1		T182	1
auto[1]	values[0]	values[2]	5	1			T168	1		T37	3		T257	1
auto[1]	values[0]	values[3]	9	1			T1	1		T12	1		T24	2
auto[1]	values[0]	values[4]	9	1			T61	3		T193	1		T218	3
auto[1]	values[0]	values[5]	6	1			T270	1		T240	2		T271	3
auto[1]	values[0]	values[6]	19	1			T14	3		T255	2		T127	2
auto[1]	values[0]	values[7]	7	1			T176	1		T195	1		T272	1
auto[1]	values[1]	values[0]	9	1			T181	4		T273	2		T274	1
auto[1]	values[1]	values[1]	11	1			T12	4		T60	1		T218	1
auto[1]	values[1]	values[2]	5	1			T181	1		T275	3		T37	1
auto[1]	values[1]	values[3]	8	1			T20	2		T175	3		T212	2
auto[1]	values[1]	values[4]	14	1			T12	1		T168	3		T205	1
auto[1]	values[1]	values[5]	6	1			T190	1		T178	1		T167	3
auto[1]	values[1]	values[6]	11	1			T127	1		T176	2		T172	2
auto[1]	values[1]	values[7]	14	1			T127	4		T227	2		T178	4
auto[1]	values[2]	values[0]	8	1			T127	2		T181	1		T246	2
auto[1]	values[2]	values[1]	7	1			T60	2		T276	2		T178	2
auto[1]	values[2]	values[2]	9	1			T1	1		T61	1		T175	2
auto[1]	values[2]	values[3]	5	1			T14	1		T61	3		T168	1
auto[1]	values[2]	values[4]	1	1			T178	1		-	-		-	-
auto[1]	values[2]	values[5]	10	1			T5	2		T168	1		T218	2
auto[1]	values[2]	values[6]	7	1			T5	1		T46	1		T44	1
auto[1]	values[2]	values[7]	9	1			T2	1		T272	1		T178	1
auto[1]	values[3]	values[0]	5	1			T44	1		T256	2		T277	1
auto[1]	values[3]	values[1]	3	1			T62	1		T109	2		-	-
auto[1]	values[3]	values[2]	7	1			T203	4		T278	1		T279	1
auto[1]	values[3]	values[3]	2	1			T127	1		T205	1		-	-
auto[1]	values[3]	values[4]	9	1			T272	1		T276	2		T273	2
auto[1]	values[3]	values[5]	3	1			T251	1		T257	2		-	-
auto[1]	values[3]	values[6]	5	1			T256	1		T257	1		T280	3
auto[1]	values[3]	values[7]	7	1			T190	1		T276	1		T239	4
auto[1]	values[4]	values[0]	9	1			T168	3		T241	3		T178	2
auto[1]	values[4]	values[1]	6	1			T174	1		T36	1		T37	4
auto[1]	values[4]	values[2]	13	1			T143	1		T61	1		T205	1
auto[1]	values[4]	values[3]	12	1			T1	2		T62	3		T252	2
auto[1]	values[4]	values[4]	18	1			T267	6		T62	4		T169	6
auto[1]	values[4]	values[5]	11	1			T47	2		T60	1		T161	2
auto[1]	values[4]	values[6]	17	1			T61	3		T128	2		T62	4
auto[1]	values[4]	values[7]	4	1			T44	1		T166	2		T37	1
auto[1]	values[5]	values[0]	23	1			T45	2		T60	2		T181	1
auto[1]	values[5]	values[1]	5	1			T185	1		T251	2		T281	2
auto[1]	values[5]	values[2]	9	1			T2	1		T44	2		T142	1
auto[1]	values[5]	values[3]	4	1			T127	2		T133	2		-	-
auto[1]	values[5]	values[4]	15	1			T2	2		T14	1		T227	2
auto[1]	values[5]	values[5]	12	1			T256	5		T182	2		T282	3
auto[1]	values[5]	values[6]	5	1			T44	1		T142	1		T205	1
auto[1]	values[5]	values[7]	16	1			T198	2		T193	1		T175	6
auto[1]	values[6]	values[0]	1	1			T273	1		-	-		-	-
auto[1]	values[6]	values[1]	10	1			T14	1		T46	1		T144	1
auto[1]	values[6]	values[2]	6	1			T12	1		T175	1		T181	2
auto[1]	values[6]	values[3]	7	1			T14	1		T44	1		T249	2
auto[1]	values[6]	values[4]	16	1			T10	2		T198	1		T62	6
auto[1]	values[6]	values[5]	8	1			T275	2		T36	1		T178	2
auto[1]	values[6]	values[6]	4	1			T202	4		-	-		-	-
auto[1]	values[6]	values[7]	6	1			T186	1		T273	2		T283	3
auto[1]	values[7]	values[0]	11	1			T190	3		T249	5		T182	2
auto[1]	values[7]	values[1]	6	1			T20	2		T198	3		T277	1
auto[1]	values[7]	values[2]	10	1			T24	3		T185	2		T273	3
auto[1]	values[7]	values[3]	8	1			T144	1		T201	2		T284	4
auto[1]	values[7]	values[4]	20	1			T44	1		T142	2		T60	1
auto[1]	values[7]	values[5]	6	1			T195	2		T260	1		T282	3
auto[1]	values[7]	values[6]	10	1			T198	1		T168	2		T285	2
auto[1]	values[7]	values[7]	12	1			T61	4		T258	2		T272	1