Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1675

1

T2

6

T4

11

T5

10

auto[1]

1709

1

T2

2

T4

7

T5

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1848

1

T2

8

T4

16

T5

10

auto[1]

1536

1

T4

2

T5

5

T22

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2656

1

T2

6

T4

14

T5

11

auto[1]

728

1

T2

2

T4

4

T5

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	680	1			T4	1		T5	3		T31	3
valid[1]	667	1			T2	1		T4	2		T5	3
valid[2]	717	1			T2	4		T4	6		T5	3
valid[3]	699	1			T2	1		T4	6		T5	2
valid[4]	621	1			T2	2		T4	3		T5	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	115	1			T5	1		T31	1		T23	1
auto[0]	auto[0]	valid[0]	auto[1]	159	1			T5	1		T26	2		T46	1
auto[0]	auto[0]	valid[1]	auto[0]	121	1			T4	2		T5	1		T31	2
auto[0]	auto[0]	valid[1]	auto[1]	145	1			T22	1		T26	3		T33	1
auto[0]	auto[0]	valid[2]	auto[0]	124	1			T2	1		T4	3		T5	1
auto[0]	auto[0]	valid[2]	auto[1]	130	1			T5	1		T22	1		T26	2
auto[0]	auto[0]	valid[3]	auto[0]	105	1			T2	1		T4	3		T5	1
auto[0]	auto[0]	valid[3]	auto[1]	163	1			T4	2		T5	1		T26	3
auto[0]	auto[0]	valid[4]	auto[0]	92	1			T2	2		T5	2		T31	1
auto[0]	auto[0]	valid[4]	auto[1]	144	1			T5	1		T23	1		T26	5
auto[0]	auto[1]	valid[0]	auto[0]	122	1			T4	1		T31	2		T23	1
auto[0]	auto[1]	valid[0]	auto[1]	149	1			T5	1		T23	1		T26	5
auto[0]	auto[1]	valid[1]	auto[0]	104	1			T2	1		T31	1		T23	1
auto[0]	auto[1]	valid[1]	auto[1]	141	1			T26	3		T33	2		T68	1
auto[0]	auto[1]	valid[2]	auto[0]	113	1			T2	1		T4	1		T31	1
auto[0]	auto[1]	valid[2]	auto[1]	199	1			T23	1		T26	3		T33	6
auto[0]	auto[1]	valid[3]	auto[0]	124	1			T23	2		T27	1		T68	1
auto[0]	auto[1]	valid[3]	auto[1]	150	1			T26	3		T46	1		T16	1
auto[0]	auto[1]	valid[4]	auto[0]	100	1			T4	2		T22	1		T23	2
auto[0]	auto[1]	valid[4]	auto[1]	156	1			T23	1		T26	3		T303	1
auto[1]	auto[0]	valid[0]	auto[0]	76	1			T41	2		T15	1		T46	1
auto[1]	auto[0]	valid[1]	auto[0]	84	1			T23	1		T41	2		T67	1
auto[1]	auto[0]	valid[2]	auto[0]	77	1			T2	2		T22	3		T42	1
auto[1]	auto[0]	valid[3]	auto[0]	77	1			T22	1		T42	1		T41	1
auto[1]	auto[0]	valid[4]	auto[0]	63	1			T4	1		T67	1		T68	1
auto[1]	auto[1]	valid[0]	auto[0]	59	1			T15	2		T67	1		T46	1
auto[1]	auto[1]	valid[1]	auto[0]	72	1			T5	2		T22	1		T27	1
auto[1]	auto[1]	valid[2]	auto[0]	74	1			T4	2		T5	1		T31	1
auto[1]	auto[1]	valid[3]	auto[0]	80	1			T4	1		T31	2		T22	1
auto[1]	auto[1]	valid[4]	auto[0]	66	1			T5	1		T22	2		T27	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal