Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	902	1			T15	20		T17	17		T18	7
all_values[1]	902	1			T15	20		T17	17		T18	7
all_values[2]	902	1			T15	20		T17	17		T18	7
all_values[3]	902	1			T15	20		T17	17		T18	7
all_values[4]	902	1			T15	20		T17	17		T18	7
all_values[5]	902	1			T15	20		T17	17		T18	7
all_values[6]	902	1			T15	20		T17	17		T18	7
all_values[7]	902	1			T15	20		T17	17		T18	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3864

1

T15

84

T17

79

T18

27

auto[1]

3352

1

T15

76

T17

57

T18

29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2859

1

T15

67

T17

55

T18

21

auto[1]

4357

1

T15

93

T17

81

T18

35

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4136

1

T15

92

T17

75

T18

30

auto[1]

3080

1

T15

68

T17

61

T18

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	188	1			T15	8		T17	7		T19	5
all_values[0]	auto[0]	auto[0]	auto[1]	99	1			T17	2		T18	2		T19	4
all_values[0]	auto[0]	auto[1]	auto[0]	158	1			T15	5		T17	3		T19	1
all_values[0]	auto[0]	auto[1]	auto[1]	87	1			T15	3		T17	1		T19	1
all_values[0]	auto[1]	auto[0]	auto[1]	199	1			T15	2		T17	1		T18	3
all_values[0]	auto[1]	auto[1]	auto[1]	171	1			T15	2		T17	3		T18	2
all_values[1]	auto[0]	auto[0]	auto[0]	175	1			T15	4		T17	4		T18	4
all_values[1]	auto[0]	auto[0]	auto[1]	96	1			T15	1		T17	1		T18	1
all_values[1]	auto[0]	auto[1]	auto[0]	158	1			T15	3		T17	2		T18	1
all_values[1]	auto[0]	auto[1]	auto[1]	93	1			T15	2		T19	1		T20	2
all_values[1]	auto[1]	auto[0]	auto[1]	195	1			T15	5		T17	7		T18	1
all_values[1]	auto[1]	auto[1]	auto[1]	185	1			T15	5		T17	3		T19	3
all_values[2]	auto[0]	auto[0]	auto[0]	174	1			T15	3		T17	2		T19	7
all_values[2]	auto[0]	auto[0]	auto[1]	89	1			T15	2		T17	4		T19	1
all_values[2]	auto[0]	auto[1]	auto[0]	156	1			T15	2		T17	5		T18	2
all_values[2]	auto[0]	auto[1]	auto[1]	79	1			T15	2		T17	1		T18	1
all_values[2]	auto[1]	auto[0]	auto[1]	227	1			T15	7		T17	3		T18	1
all_values[2]	auto[1]	auto[1]	auto[1]	177	1			T15	4		T17	2		T18	3
all_values[3]	auto[0]	auto[0]	auto[0]	176	1			T15	2		T17	4		T18	1
all_values[3]	auto[0]	auto[0]	auto[1]	109	1			T15	1		T17	2		T19	6
all_values[3]	auto[0]	auto[1]	auto[0]	129	1			T15	3		T17	1		T18	2
all_values[3]	auto[0]	auto[1]	auto[1]	105	1			T15	3		T18	1		T19	1
all_values[3]	auto[1]	auto[0]	auto[1]	210	1			T15	4		T17	6		T19	4
all_values[3]	auto[1]	auto[1]	auto[1]	173	1			T15	7		T17	4		T18	3
all_values[4]	auto[0]	auto[0]	auto[0]	185	1			T15	4		T17	3		T18	1
all_values[4]	auto[0]	auto[0]	auto[1]	72	1			T15	2		T17	1		T19	5
all_values[4]	auto[0]	auto[1]	auto[0]	159	1			T15	1		T17	2		T18	3
all_values[4]	auto[0]	auto[1]	auto[1]	93	1			T15	4		T17	3		T18	1
all_values[4]	auto[1]	auto[0]	auto[1]	202	1			T15	3		T17	6		T18	2
all_values[4]	auto[1]	auto[1]	auto[1]	191	1			T15	6		T17	2		T19	5
all_values[5]	auto[0]	auto[0]	auto[0]	290	1			T15	8		T17	5		T18	3
all_values[5]	auto[0]	auto[1]	auto[0]	230	1			T15	9		T17	4		T18	1
all_values[5]	auto[1]	auto[0]	auto[1]	200	1			T15	2		T17	1		T18	2
all_values[5]	auto[1]	auto[1]	auto[1]	182	1			T15	1		T17	7		T18	1
all_values[6]	auto[0]	auto[0]	auto[0]	193	1			T15	4		T17	2		T19	3
all_values[6]	auto[0]	auto[0]	auto[1]	99	1			T17	1		T19	4		T20	1
all_values[6]	auto[0]	auto[1]	auto[0]	152	1			T15	2		T17	4		T18	3
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T15	3		T17	1		T19	2
all_values[6]	auto[1]	auto[0]	auto[1]	213	1			T15	7		T17	8		T18	1
all_values[6]	auto[1]	auto[1]	auto[1]	175	1			T15	4		T17	1		T18	3
all_values[7]	auto[0]	auto[0]	auto[0]	190	1			T15	5		T17	4		T19	7
all_values[7]	auto[0]	auto[0]	auto[1]	83	1			T15	1		T17	2		T18	3
all_values[7]	auto[0]	auto[1]	auto[0]	146	1			T15	4		T17	3		T19	3
all_values[7]	auto[0]	auto[1]	auto[1]	103	1			T15	1		T17	1		T19	1
all_values[7]	auto[1]	auto[0]	auto[1]	200	1			T15	9		T17	3		T18	2
all_values[7]	auto[1]	auto[1]	auto[1]	180	1			T17	4		T18	2		T19	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal