Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45981

1

T2

168

T4

330

T5

349

auto[1]

16585

1

T4

39

T5

85

T22

87

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45724

1

T2

125

T4

247

T5

289

auto[1]

16842

1

T2

43

T4

122

T5

145

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32018	1			T2	86		T4	183		T5	202
others[1]	5257	1			T2	12		T4	30		T5	36
others[2]	5230	1			T2	13		T4	41		T5	37
others[3]	6125	1			T2	17		T4	34		T5	38
interest[1]	3476	1			T2	8		T4	23		T5	30
interest[4]	20897	1			T2	55		T4	111		T5	133
interest[64]	10460	1			T2	32		T4	58		T5	91

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14859	1			T2	68		T4	117		T5	99
auto[0]	auto[0]	others[1]	2520	1			T2	9		T4	17		T5	18
auto[0]	auto[0]	others[2]	2423	1			T2	11		T4	17		T5	12
auto[0]	auto[0]	others[3]	2829	1			T2	9		T4	18		T5	20
auto[0]	auto[0]	interest[1]	1638	1			T2	6		T4	11		T5	17
auto[0]	auto[0]	interest[4]	9709	1			T2	45		T4	73		T5	64
auto[0]	auto[0]	interest[64]	4870	1			T2	22		T4	28		T5	38
auto[0]	auto[1]	others[0]	8680	1			T4	16		T5	34		T22	38
auto[0]	auto[1]	others[1]	1350	1			T4	4		T5	9		T22	8
auto[0]	auto[1]	others[2]	1395	1			T4	8		T5	11		T22	13
auto[0]	auto[1]	others[3]	1621	1			T4	6		T5	8		T22	11
auto[0]	auto[1]	interest[1]	880	1			T4	1		T5	4		T22	4
auto[0]	auto[1]	interest[4]	5768	1			T4	10		T5	23		T22	23
auto[0]	auto[1]	interest[64]	2659	1			T4	4		T5	19		T22	13
auto[1]	auto[0]	others[0]	8479	1			T2	18		T4	50		T5	69
auto[1]	auto[0]	others[1]	1387	1			T2	3		T4	9		T5	9
auto[1]	auto[0]	others[2]	1412	1			T2	2		T4	16		T5	14
auto[1]	auto[0]	others[3]	1675	1			T2	8		T4	10		T5	10
auto[1]	auto[0]	interest[1]	958	1			T2	2		T4	11		T5	9
auto[1]	auto[0]	interest[4]	5420	1			T2	10		T4	28		T5	46
auto[1]	auto[0]	interest[64]	2931	1			T2	10		T4	26		T5	34

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal