Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2439744	1			T1	1		T2	1		T3	519
all_values[1]	2439744	1			T1	1		T2	1		T3	519
all_values[2]	2439744	1			T1	1		T2	1		T3	519
all_values[3]	2439744	1			T1	1		T2	1		T3	519
all_values[4]	2439744	1			T1	1		T2	1		T3	519
all_values[5]	2439744	1			T1	1		T2	1		T3	519
all_values[6]	2439744	1			T1	1		T2	1		T3	519
all_values[7]	2439744	1			T1	1		T2	1		T3	519

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19232744

1

T1

8

T2

8

T3

4152

auto[1]

285208

1

T21

94

T66

601

T26

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19494008

1

T1

8

T2

8

T3

4152

auto[1]

23944

1

T5

34

T8

378

T17

212

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2411812	1			T1	1		T2	1		T3	519
all_values[0]	auto[0]	auto[1]	11308	1			T5	34		T8	173		T17	96
all_values[0]	auto[1]	auto[0]	16183	1			T21	11		T66	1		T26	4
all_values[0]	auto[1]	auto[1]	441	1			T21	2		T66	2		T26	1
all_values[1]	auto[0]	auto[0]	2401875	1			T1	1		T2	1		T3	519
all_values[1]	auto[0]	auto[1]	7001	1			T8	133		T17	70		T20	11
all_values[1]	auto[1]	auto[0]	30371	1			T21	7		T66	1		T26	2
all_values[1]	auto[1]	auto[1]	497	1			T21	3		T66	2		T26	2
all_values[2]	auto[0]	auto[0]	2409231	1			T1	1		T2	1		T3	519
all_values[2]	auto[0]	auto[1]	2530	1			T8	72		T17	46		T54	28
all_values[2]	auto[1]	auto[0]	27692	1			T21	7		T66	2		T26	3
all_values[2]	auto[1]	auto[1]	291	1			T21	1		T66	1		T26	2
all_values[3]	auto[0]	auto[0]	2371679	1			T1	1		T2	1		T3	519
all_values[3]	auto[0]	auto[1]	192	1			T21	3		T66	2		T26	2
all_values[3]	auto[1]	auto[0]	67682	1			T21	6		T66	193		T26	1
all_values[3]	auto[1]	auto[1]	191	1			T21	3		T66	2		T26	1
all_values[4]	auto[0]	auto[0]	2407425	1			T1	1		T2	1		T3	519
all_values[4]	auto[0]	auto[1]	187	1			T21	5		T66	2		T30	6
all_values[4]	auto[1]	auto[0]	31937	1			T21	12		T66	2		T26	5
all_values[4]	auto[1]	auto[1]	195	1			T21	4		T30	2		T31	4
all_values[5]	auto[0]	auto[0]	2391312	1			T1	1		T2	1		T3	519
all_values[5]	auto[0]	auto[1]	163	1			T21	3		T66	1		T26	2
all_values[5]	auto[1]	auto[0]	48080	1			T21	12		T66	193		T26	1
all_values[5]	auto[1]	auto[1]	189	1			T21	4		T66	4		T30	2
all_values[6]	auto[0]	auto[0]	2411266	1			T1	1		T2	1		T3	519
all_values[6]	auto[0]	auto[1]	183	1			T21	4		T66	1		T30	4
all_values[6]	auto[1]	auto[0]	28099	1			T21	6		T66	193		T26	1
all_values[6]	auto[1]	auto[1]	196	1			T21	5		T66	3		T26	1
all_values[7]	auto[0]	auto[0]	2406389	1			T1	1		T2	1		T3	519
all_values[7]	auto[0]	auto[1]	191	1			T21	4		T66	2		T26	1
all_values[7]	auto[1]	auto[0]	32975	1			T21	7		T66	2		T26	2
all_values[7]	auto[1]	auto[1]	189	1			T21	4		T26	2		T30	1